Shift register unit comprising input circuit, first control circuit, blanking control circuit, first output circuit, and second output circuit, driving method, gate driving circuit, and display device

A shift register unit, comprising:

• an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit,
• wherein the input circuit is electrically connected to an input terminal and a first node, and is configured to control a level of the first node in response to an input signal input from the input terminal;
• the first control circuit is electrically connected to the input terminal, the first node, and a second node, and is configured to control a level of the second node in response to the input signal input from the input terminal;
• the blanking control circuit is electrically connected to a selection control terminal, a first clock signal terminal, the first node and the second node, and is configured to control the level of the first node and the level of the second node under control of a selection control signal input from the selection control terminal, a first clock signal input from the first clock signal terminal;
• the first output circuit comprises a first output terminal and the first node, and the first output circuit is configured to output a first output signal at the first output terminal under control of the level of the first node;
• and
• the second output circuit comprises a second output terminal and the second node, and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node,
• wherein in a case where the first output terminal comprises a shift output terminal and a scan signal output terminal, the first output circuit comprises a fifth transistor, a sixth transistor, and a second capacitor;
• a gate electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to a second clock signal terminal to receive a second clock signal as the first output signal, and a second electrode of the fifth transistor is electrically connected to the shift output terminal;
• a gate electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to a third clock signal terminal to receive a third clock signal as the first output signal, and a second electrode of the sixth transistor is electrically connected to the scan signal output terminal;
• and
• a first electrode of the second capacitor is electrically connected to the first node, and a second electrode of the second capacitor is electrically connected to the second electrode of the fifth transistor or the second electrode of the sixth transistor,
• wherein the second output circuit comprises a seventh transistor and a third capacitor;
• a gate electrode of the seventh transistor is electrically connected to the second node, a first electrode of the seventh transistor is electrically connected to a fourth clock signal terminal to receive a fourth clock signal as the second output signal, and a second electrode of the seventh transistor is electrically connected to the second output terminal;
• and
• a first electrode of the third capacitor is electrically connected to the second node, and a second electrode of the third capacitor is electrically connected to the second output terminal;
• a duration in a case where the third clock signal and the fourth clock signal are simultaneously at a high level is less than or equal to a duration in a case where the third clock signal and the fourth clock signal are neither simultaneously at a high level nor a low level.

A shift register unit, comprising:

• an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit,
• wherein the input circuit is electrically connected to an input terminal and a first node, and is configured to control a level of the first node in response to an input signal input from the input terminal;
• the first control circuit is electrically connected to the input terminal, the first node, and a second node, and is configured to control a level of the second node in response to the input signal input from the input terminal;
• the blanking control circuit is electrically connected to a selection control terminal, a first clock signal terminal, the first node and the second node, and is configured to control the level of the first node and the level of the second node under control of a selection control signal input from the selection control terminal, a first clock signal input from the first clock signal terminal;
• the first output circuit comprises a first output terminal and the first node, and the first output circuit is configured to output a first output signal at the first output terminal under control of the level of the first node;
• and
• the second output circuit comprises a second output terminal and the second node, and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node,
• wherein the first output terminal comprises a shift output terminal and at least one scan signal output terminal;
• the shift output terminal, the at least one scan signal output terminal first output terminal and the blanking control circuit correspond to a same row of pixel.