Transactionally deterministic high speed financial exchange having improved, efficiency, communication, customization, performance, access, trading opportunities, credit controls, and fault tolerance

A system comprising:

• a plurality of hardware match engines coupled with a processor external thereto, each of which is unable to access unsatisfied orders of the others, the processor further coupled with a memory which stores computer executable instructions which, when executed by the processor, cause the processor to implement an implicator coupled with each of the plurality of hardware match engines and operative to receive data from each of the plurality of hardware match engines indicative of results of attempts by that hardware match engine to satisfy incoming orders received thereby, each for a transaction of at least one financial instrument and store the received data in the memory indicative of all unsatisfied incoming orders of all of the plurality of hardware match engines, identify, using the data stored in the memory when the received data from one of the plurality of hardware match engines indicates that it was unable to fully satisfy an incoming order received thereby, data stored in the memory indicative of any unsatisfied orders, received by at least one other of the plurality of match engines, wherein a transaction between the incoming order and/or any of the identified unsatisfied orders would at least partially satisfy the incoming order and/or any of the identified unsatisfied orders, and determine that the incoming order together with the identified unsatisfied orders, if the transaction therebetween were to be completed, would fully satisfy the incoming order and the identified unsatisfied orders;
• and
• wherein the computer executable instructions are further executable by the processor to cause the processor to implement an order generator coupled with the implicator and operative to generate, based on the determination, a set of synthetic counter orders, the set comprising a synthetic counter order for a transaction counter to the incoming order and synthetic counter orders counter to each of the identified unsatisfied orders, and submit each generated synthetic counter order to those hardware match engines of the plurality of hardware match engines which received the incoming and identified unsatisfied orders for which the synthetic counter order is counter thereto, each of which processes the synthetic order in a same manner as an incoming order thereto.

A computer implemented method comprising:

• providing a plurality of hardware match engines coupled with a processor external thereto, each of which is unable to access unsatisfied orders of the others;
• receiving, by a processor, data from each of the plurality of hardware match engines indicative of results of attempts by that hardware match engine to satisfy incoming orders received thereby, each for a transaction of at least one financial instrument and storing the received data in a memory coupled with the processor indicative of all unsatisfied incoming orders of all of the plurality of hardware match engines;
• identifying, by the processor using the data stored in the memory when the received data from one of the plurality of hardware match engines indicates that it was unable to fully satisfy an incoming order received thereby, data stored in the memory indicative of any unsatisfied orders, received by at least one other of the plurality of match engines, wherein a transaction between the incoming order and/or any of the identified unsatisfied orders would at least partially satisfy the incoming order and/or any of the identified unsatisfied orders;
• determining, by the processor, that the incoming order together with the identified unsatisfied orders, if the transaction therebetween were to be completed, would fully satisfy the incoming order and the identified unsatisfied orders;
• and
• generating, by the processor based on the determination, a set of synthetic counter orders, the set comprising a synthetic counter order for a transaction counter to the incoming order and synthetic counter orders counter to each of the identified unsatisfied orders, and submitting each generated synthetic counter order to those hardware match engines of the plurality of hardware match engines which received the incoming and identified unsatisfied orders for which the synthetic counter order is counter thereto, each of which processes the synthetic order in a same manner as an incoming order thereto.