Systems and methods for coordinating processing of instructions across multiple components

A computer system comprising:

• first and second processors each operative to execute designated computer executable instructions only upon subsequent separate receipt of a corresponding instruction identifier, the first and second processors each further configured to:
• receive a designated computer executable instruction and a first instruction identifier corresponding to the designated computer executable instruction from a first source;
• store the received designated computer executable instruction, in association with the first instruction identifier, in first and second memories coupled with the first and second processors respectively;
• receive, from a second source subsequent to the storage of the received designated computer executable instruction, a second instruction identifier corresponding to the designated computer executable instruction;
• upon receiving the second instruction identifier from the second source, retrieve, from the first and second memories respectively using the received second instruction identifier, the previously stored designated computer executable instruction associated with the first instruction identifier which corresponds to the second instruction identifiers;
• and
• execute the retrieved designated computer executable instruction;
• and
• wherein the execution of the retrieved designated computer executable instruction by both the first and second processors is coordinated with respect to the receipt of the second instruction identifier even when the second instruction identifier is not received by the first and second processors at the same time.

A computer system comprising:

• means for receiving from a first source, by first and second processors, each operative to execute designated computer executable instructions only upon subsequent separate receipt of a corresponding instruction identifier, a designated computer executable instruction and a first instruction identifier corresponding to the designated computer executable instruction;
• means for storing, upon receipt, the received designated computer executable instruction, in association with the first instruction identifier, in first and second memories coupled with the first and second processors respectively;
• means for receiving, subsequent to the storing, by each of the first and second processors from a second source, a second instruction identifier which corresponds to the first instruction identifier associated with the stored designated computer executable instruction;
• means for, upon receiving the second instruction identifier from the second source, retrieving from the respective of the first and second memories by each of the first and second processors, using the received second instruction identifier, the designated computer executable instruction associated with the first instruction identifier which corresponds to the received second instruction identifier;
• and
• means for executing, subsequent to the retrieving by each of the first and second processors, the retrieved designated computer executable instruction;
• and
• wherein the execution of the retrieved designated computer executable instruction by both the first and second processors is coordinated with respect to the receipt of the second instruction identifier even when the second instruction identifier is not received by the first and second processors at the same time.