Method for analog in-memory compute for neural networks

A system for analog in-memory compute for a neural network comprising:

• an array of neurons, wherein each neuron of the array of neurons receives a pulse of magnitude xi, and duration t, wherein a product xi*yi provides a current proportional to the input for a time duration t, which is a charge associated with a particular neuron in response to the input being presented to that particular neuron;
• A reference cell comprising a gate-drain connected flash cell configuration and coupled with the array of neurons, wherein the reference cell is programmed to a pre-determined threshold voltage Vt-ref, wherein the reference cell receives a pre-determined current, Iref, wherein, based on the Iref and a pre-determined threshold voltage Vt-ref, a voltage is created at a drain of the reference cell, and wherein the voltage is then buffered with an operational amplifier that generates a control gate voltage VCG that is provided to the control gates of an array of neurons;
• and
• a set of analog to digital converters (ADCs), wherein each column of neurons of the array of neurons has an ADC, wherein an ADC is coupled with a sense node, wherein a current is used to pre-charge a bit-line of a neuron of the array of neurons and the sense node is used to sense the total charge discharged through the bit line of the neural array over a predetermined amount of time,
• wherein when the neural array is placed in an on state and the current flows, the value of the current flowing is a function of a control gate bias generated from the reference array and Vt of the neuron,
• wherein a pulse-width of a select gate of the reference cell determines a time each neural cell of the neural array is turned on and the amount of charge removed from the sense-node capacitor,
• wherein when the sense node discharges and reaches a trip point of a detector of the sense node, the detector then provides a pulse signal, and
• wherein the pulse signal is counted by a counter coupled with the detector, wherein the counter registers a set of discharge cycles of the sense node.