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US 11,687,759 B2Granted
Neural network accelerator
AssigneeSemiconductor Components Industries, LLC
InventorsIvo Leonardus Coenen, Dennis Wayne Mitchler
Life of this patent
Estimating the term…
Abstract
A neural network implementation is disclosed. The implementation allows the computations for the neural network to be performed on either an accelerator or a processor. The accelerator and the processor share a memory and communicate over a bus to perform the computations and to share data. The implementation uses weight compression and pruning, as well as parallel processing, to reduce computing, storage, and power requirements.
Claims10
A method for implementing a neural network, the method comprising:
- receiving input data;
- fetching, from a memory, weights of the neural network;
- performing a first portion of processing for the neural network, the first portion implemented in hardware by an accelerator including a plurality of parallel multiply and accumulate (MAC) units configured to perform a plurality of MAC operations to generate a first neuron value at a first accumulator and a second neuron value at a second accumulator, wherein the first portion includes:
- receiving a first subset of the input data from a circular buffer at inputs of the plurality of parallel MAC units;
- performing the plurality of parallel MAC operations using a first set of weights, while holding the inputs of the plurality of parallel MAC units stable at the first subset of the input data, to generate a first portion of the first neuron value at the first accumulator;
- performing the plurality of parallel MAC operations using a second set of weights, while holding the inputs of the plurality of parallel MAC units stable at the first subset of the input data, to generate a second portion of the second neuron value at the second accumulator;
- repeating receiving subsets of input data from the circular buffer and performing the plurality of parallel MAC operations while holding the inputs of the plurality of parallel MAC units stable to accumulate the first neuron value at the first accumulator and the second neuron value at the second accumulator for all input data;
- selecting the first neuron value before a bias and an activation function is applied, using a multiplexer coupled to the plurality of parallel MAC units;
- and
- writing the first neuron value to the memory;
- and
- performing a second portion of processing for the neural network, the second portion implemented in software by a processor, the accelerator and the processor using a bus to communicate and to share access to the memory, wherein the second portion includes:
- reading the first neuron value from the memory;
- and
- applying the bias and the activation function to the first neuron value.
12 more elements
Dependencies are inferred from the claim text.