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US 11,687,679 B2Granted
Current flattening circuit for protection against power side channel attacks
AssigneeNVIDIA Corporation
InventorsNikola Nedovic, Sudhir Shrikantha Kudva
Life of this patent
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Abstract
Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
Claims13
A current flattening circuit comprising:
- at least one PMOS transistor interposed between a power supply and a load;
- a shunt transistor and a differential amplifier each coupled to a node between the at least one PMOS transistor and the load;
- and
- a gate voltage of the shunt transistor configured to be controlled by the differential amplifier.
1 more element
A current flattening circuit comprising:
- a shunt transistor coupled to receive current directly from a power supply and configured with a fixed gate bias voltage;
- a load current sensor coupled to directly receive the current from the power supply and to supply current directly to a load;
- and
- a differential amplifier coupled across the load current sensor to control a gate of the shunt transistor.
1 more element
A current flattening circuit comprising:
- a load current sensor interposed between a power supply and a load;
- a differential high pass filter coupled across the load current sensor, the differential high pass filter having a gain;
- a differential amplifier coupled to outputs of the differential high pass filter;
- and
- the differential amplifier coupled to drive a gate of a shunt transistor of the load.
2 more elements
Dependencies are inferred from the claim text.