Signaling mechanism for bus inversion
AssigneeMicron Technology, Inc.
InventorsStephen D. Hanna, Jonathan S. Parry
Life of this patent
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Abstract
Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.
Claims20
An apparatus, comprising:
- a controller configured to transmit a command to a memory device via a bus;
- a buffer configured to transmit, to the memory device, a signal enabling reception of the command at the memory device via a control line;
- and
- an inversion circuit configured to:
- detect, after a transmission of the signal, a voltage level of the control line indicating whether a set of data on the bus is in an inverted state,
- obtain the set of data from the bus, and
- invert the set of data to obtain corresponding uninverted data based at least in part on the voltage level of the control line indicating that the set of data is in the inverted state.
An apparatus, comprising:
- a controller configured to transmit a command to a memory device via a bus;
- a buffer configured to transmit, to the memory device, a first signal enabling reception of the command at the memory device via a control line;
- and
- an inversion circuit configured to:
- invert, based at least in part on a content of a set of data associated with the command, the set of data to put the set of data into an inverted state, and
- apply, to logic based at least in part on inverting the set of data, a second signal indicating that the set of data is in the inverted state,
- wherein the logic is configured to apply, based at least in part on the second signal, a voltage level to the buffer, the voltage level indicating that the set of data is in the inverted state, and
- wherein the inversion circuit is further configured to transmit, after inversion of the set of data, the set of data to the memory device via the bus.
An apparatus, comprising:
- a memory array;
- logic configured to receive, from a first controller, a signal enabling reception of a command via a control line;
- a second controller configured to:
- receive, based at least in part on the signal, the command via a bus that is coupled with the first controller and the second controller, and
- retrieve, based at least in part on the command, a set of data from the memory array;
- and
- an inversion circuit configured to apply, to the control line and based at least in part on a content of the set of data, a voltage indicating whether the set of data is in an inverted state.
Dependencies are inferred from the claim text.