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US 11,687,469 B2Granted
Host-resident translation layer validity check techniques
AssigneeMicron Technology, Inc.
InventorDavid Aaron Palmer
Life of this patent
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Abstract
Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.
Claims19
A method comprising:
- receiving, at a memory system, a memory request from a host, the memory request including a logical block address (LBA) associated with the host and a first representation of a physical address associated with the memory system;
- decrypting the first representation of the physical address at a decryption circuit using a key of the memory system to provide a second representation of the physical address, wherein decrypting the first representation of the physical address includes:
- applying a decryption algorithm to the first representation using the key to provide a decrypted representation of the first representation;
- determining the decrypted representation is not a valid physical address of the memory system;
- determining a correct physical address of the memory system associated with the LBA received from the host using memory system-resident mapping information;
- and
- executing the memory request using the correct physical address.
4 more elements
A memory system comprising:
- a controller, configured to perform operations comprising:
- receiving a memory request from a host, the memory request including a logical block address (LBA) associated with the host and a first representation of a physical address associated with the memory system;
- decrypting the first representation of the physical address at a decryption circuit using a key of the memory system to provide a second representation of the physical address, wherein decrypting the first representation of the physical address includes:
- applying a decryption algorithm to the first representation using the key to provide a decrypted representation of the first representation;
- determining the decrypted representation is not a valid physical address of the memory system;
- determining a correct physical address of the memory system associated with the LBA received from the host using memory system-resident mapping information;
- and
- executing the memory request using the correct physical address.
5 more elements
A non-transitory machine-readable medium, storing instructions, which when executed by a controller of a memory system, cause the controller to perform operations comprising:
- receiving a memory request from a host, the memory request including a logical block address (LBA) associated with the host and a first representation of a physical address associated with the memory system;
- decrypting the first representation of the physical address at a decryption circuit using a key of the memory system to provide a second representation of the physical address, wherein decrypting the first representation of the physical address includes:
- applying a decryption algorithm to the first representation using the key to provide a decrypted representation of the first representation;
- determining the decrypted representation is not a valid physical address of the memory system;
- determining a correct physical address of the memory system associated with the LBA received from the host using memory system-resident mapping information;
- and
- executing the memory request using the correct physical address.
4 more elements
Dependencies are inferred from the claim text.