US 11,687,466 B1Granted

Translation lookaside buffer consistency directory for use with virtually-indexed virtually-tagged first level data cache that holds page table permissions

AssigneeVentana Micro Systems Inc.

InventorsJohn G. Favor, Srivatsan Srinivasan

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Abstract

A virtually-indexed and virtually-tagged cache has E entries each holding a memory line at a physical memory line address (PMLA), a tag of a virtual memory line address (VMLA), and permissions of a memory page that encompasses the PMLA. A directory having E corresponding entries is physically arranged as R rows by C columns=E. Each directory entry holds a directory tag comprising hashes of corresponding portions of a page address portion of the VMLA whose tag is held in the corresponding cache entry. In response to a translation lookaside buffer management instruction (TLBMI), the microprocessor generates a target tag comprising hashes of corresponding portions of a TLBMI-specified page address. For each directory row, the microprocessor: for each directory entry of the row, compares the target and directory tags to generate a match indictor used to invalidate the corresponding cache entry.

Claims29

Dependent claims

A microprocessor, comprising:

a virtually-indexed and virtually-tagged cache having E entries, where E is the number of entries in the cache, wherein each cache entry is configured to hold:
a copy of a line of memory at a physical memory line address;
a tag of a virtual memory line address, wherein the virtual memory line address is translatable into the physical memory line address;
and
permissions associated with a page of memory that encompasses the physical memory line address;
a directory having an E number of entries corresponding to the E number of cache entries, wherein the directory is physically arranged as R rows and C columns, where R is the number of rows in the directory and C is the number of columns in the directory, wherein R*C=E, wherein each directory entry is configured to hold:
a directory tag comprising one or more hashes of corresponding one or more portions of a page address, wherein the page address is a portion of the virtual memory line address whose tag is held in the cache entry corresponding to the directory entry;
and
wherein in response to a translation lookaside buffer management instruction (TLBMI) that specifies a virtual address, the microprocessor is configured to:
generate a target tag comprising one or more hashes of corresponding one or more portions of a page address, wherein the page address is a portion of the virtual address specified by the TLBMI;
and
for each row of the R rows of the directory:
for each directory entry of the C directory entries of the row:
make a comparison of the target tag with the directory tag of the directory entry;
and
generate a match indictor based on the comparison;
and
for each directory entry having a true match indictor, invalidate the corresponding cache entry.

15 more elements

A method, comprising:

in a microprocessor comprising:
a virtually-indexed and virtually-tagged cache having E entries, where E is the number of entries in the cache, wherein each cache entry is configured to hold:
a copy of a line of memory at a physical memory line address;
a tag of a virtual memory line address, wherein the virtual memory line address is translatable into the physical memory line address;
and
permissions associated with a page of memory that encompasses the physical memory line address;
and
a directory having an E number of entries corresponding to the E number of cache entries, wherein the directory is physically arranged as R rows and C columns, where R is the number of rows in the directory and C is the number of columns in the directory, wherein R*C=E, wherein each directory entry is configured to hold:
a directory tag comprising one or more hashes of corresponding one or more portions of a page address, wherein the page address is a portion of the virtual memory line address whose tag is held in the cache entry corresponding to the directory entry;
in response to a translation lookaside buffer management instruction (TLBMI) that specifies a virtual address:
generating a target tag comprising one or more hashes of corresponding one or more portions of a page address, wherein the page address is a portion of the virtual address specified by the TLBMI;
and
for each row of the R rows of the directory:
for each directory entry of the C directory entries of the row:
making a comparison of the target tag with the directory tag of the directory entry;
and
generating a match indictor based on the comparison;
and
for each directory entry having a true match indictor:
invalidating the corresponding cache entry.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/751,972Filed 24 May 2022 · us provisional application
Priority: 12 May 2022
Granted: 27 Jun 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 12/0895
Caches characterised by their organisation or structure: of parts of caches, e.g. directory or tag array
G06F 12/1063
Associated with a data cache: the data cache being concurrently virtually addressed
G06F 12/0864
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…
G06F 12/1036
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: for multiple virtual address spaces,…