US 11,687,465 B2 · Spatial cache

Abstract

A cache includes a p-by-q array of memory units; a row addressing unit; and a column addressing unit. Each memory unit has an m-by-n array of memory cells. The column addressing unit has, for each memory unit, m n-to-one multiplexers, one associated with each of the m rows of the memory unit, wherein each n-to-one multiplexer has an input coupled to each of the n memory cells associated with the row associated with that multiplexer. The row addressing unit has, for each memory unit, n m-to-one multiplexers, one associated with each of the n columns of the memory unit, wherein each m-to-one multiplexer has an input coupled to each of the m memory cells associated with the column associated with that multiplexer. The row addressing unit and column addressing unit support reading and/or writing of the array of memory units, e.g. using virtual or physical addresses.

Claims24

Dependent claims

A cache comprising:

a p (rows)×q (columns) array of memory units;
a row addressing unit;
and
a column addressing unit;
wherein each memory unit has an m (rows)×n (columns) array of memory cells;
wherein the column addressing unit has, for each memory unit, m n-to-one multiplexers, one associated with each of the m rows of the memory unit, wherein each n-to-one multiplexer has an input coupled to each of the n memory cells associated with the row associated with that multiplexer;
wherein the row addressing unit has, for each memory unit, n m-to-one multiplexers, one associated with each of the n columns of the memory unit, wherein each m-to-one multiplexer has an input coupled to each of the m memory cells associated with the column associated with that multiplexer, and
wherein the row addressing unit and column addressing unit support reading and/or writing of the array of memory units, such that multiple rows and/or multiple columns of the array of memory units may be read and/or written in parallel.

5 more elements

The method of c1aim 19, further comprising:

moving the virtua1 origin and the operand region associated with the virtual origin;
and
initializing a second plurality of the memory units with remote memory that represents the two-dimensional data structure, such that the second plurality of the memory units represents a part of the two-dimensional data structure in response to the moving the virtual origin and the operand region associated with the virtual origin.

Dependencies are inferred from the claim text.

Spatial cache

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Spatial cache

Life of this patent

Abstract

Claims24