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US 11,687,459 B2Granted
Application of a default shared state cache coherency protocol
AssigneeHewlett Packard Enterprise Development LP
InventorsMichael Malewicki, Thomas McGee, Michael S. Woodacre
Life of this patent
Estimating the term…
Abstract
Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.
Claims17
A method comprising:
- when a memory is in a default shared state,
- tracking, by a directory associated with a first processor of a set of processors, exclusive ownership of a range of blocks of the memory;
- responsive to receiving a request from a second processor of the set of processors to read one or more blocks of memory absent from the directory, transmitting the one or more blocks in the default shared state to the second processor in a shared state without tracking the absent blocks in the directory, and
- when the memory is in a default invalid state,
- tracking the one or more blocks of the memory in a cache of the directory, wherein the one or more blocks of memory are marked as shared in the directory cache;
- and
- responsive to receiving a request from the second processor of the set of processors to read one or more blocks of memory absent from the directory, transmitting the one or more shared blocks to the second processor.
4 more elements
A system comprising:
- a memory including a first range of memory blocks in a default shared state and a second, different range of memory blocks in a default invalid state;
- a directory to track exclusive ownership of the first range of memory blocks;
- and
- a node controller associated with the memory, wherein the node controller,
- responsive to receiving a request from a processor to read one or more blocks of memory of the first range applies a shared state protocol to:
- determine whether the one or more blocks of memory of the first range are tracked in the directory;
- and
- responsive to a determination that the one or more block of memory are not present in the directory, transmit the one or more blocks of memory to the processor without tracking the absent blocks in the directory, and
- wherein the node controller, responsive to receiving a request from the second processor to read one or more blocks of memory of the second range applies an invalid state protocol to:
- determine whether the one or more blocks of memory of the second range are tracked in the directory;
- responsive to a determination that the one or more blocks of memory of the second range are not present in the directory, track the one or more blocks of memory of the second range in the directory, wherein the one or more blocks of memory are marked as shared in a cache of the directory;
- and
- transmit the one or more shared blocks to the processor.
10 more elements
An apparatus comprising:
- a node controller associated with a first processor of a set of processors and a memory and operable to enforce cache coherency for blocks of the memory,
- wherein the node controller, when in a default shared state:
- tracks exclusive ownership of a subset of the blocks of the memory in a directory of the node controller;
- and
- responsive to receiving a request from a second processor of the set of processors to read one or more blocks of memory absent from the directory, transmits the one or more blocks to the second processor in a shared state without tracking the absent blocks in the directory, and
- wherein the node controller, when in a default invalid state:
- tracks the one or more blocks of memory in a cache of the directory, wherein the one or more blocks of memory are marked as shared in the directory cache;
- and
- responsive to receiving a request from the second processor of the set of processors to read the one or more blocks of memory absent from the directory, transmits the one or more shared blocks to the second processor.
6 more elements
Dependencies are inferred from the claim text.