Hardware coherence for memory controller
AssigneeTexas Intruments Incorporated
InventorsAbhijeet Ashok Chachad, David Matthew Thompson, Naveen Bhoria
Life of this patent
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Abstract
A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.
Claims20
A circuit device comprising:
- a processor core;
- a level one (L1) cache coupled to the processor core;
- a level two (L2) cache controller coupled to the L1 cache;
- and
- a shadow L1 cache coupled to the L2 cache controller, wherein the L2 cache controller is configured to:
- receive a request to read data;
- determine whether the request is a non-coherent request or a coherent request;
- based on the request being a coherent request:
- determine whether the request is a hit or a miss in the shadow L1 cache;
- and
- based on the request being a hit in the shadow L1 cache, provide a snoop request for the data from the L1 cache;
- and
- provide a response to the request that includes the data.
A circuit device comprising:
- a processor core;
- a level one (L1) cache coupled to the processor core that includes an L1 main cache and an L1 victim cache;
- a level two (L2) cache controller coupled to the L1 cache;
- a shadow L1 cache coupled to the L2 cache controller;
- and
- a shadow L1 victim cache coupled to the L2 cache controller, wherein the L2 cache controller is configured to:
- receive a request to read data;
- determine whether the request is associated with a coherent requestor;
- based on the request being associated with the coherent requestor:
- determine whether the request is a hit or a miss in either of the shadow L1 cache and the shadow L1 victim cache;
- and
- based on the request being a hit in either of the shadow L1 cache or the shadow L1 victim cache, provide a snoop request for the data from the L1 cache;
- and
- provide a response to the request that includes the data.
Dependencies are inferred from the claim text.