Data cache with hybrid writeback and writethrough
AssigneeSiFive, Inc.
InventorsJohn Ingalls, Wesley Waylon Terpstra, Henry Cook
Life of this patent
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AssigneeSiFive, Inc.
InventorsJohn Ingalls, Wesley Waylon Terpstra, Henry Cook
Estimating the term…
Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.
A processing system comprising:
A method for performing hybrid writeback and writethrough, the method comprising:
A method for performing hybrid writeback and writethrough, the method comprising:
Dependencies are inferred from the claim text.