Memory circuit and cache circuit configuration
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
Life of this patent
Estimating the term…
Abstract
A memory circuit includes a stack of first dies including multiple sets of memory cells of a first type, a second die including multiple sets of memory cells of a second type, a third die, and an interposer carrying the first, second, and third dies. The second die includes a first set of input/output (I/O) terminals on a top surface of the second die and a second set of I/O terminals on a bottom surface of the second die. The stack of first dies is coupled to the second die through the first set of I/O terminals. The interposer is coupled to the second die through the second set of I/O terminals. The third die is positioned aside the second die and in communication with the second die through the interposer.
Claims20
A memory circuit, comprising:
- a stack of first dies, wherein the stack of first dies includes multiple sets of memory cells of a first type;
- a second die, wherein the second die includes multiple sets of memory cells of a second type, wherein the second die includes a first set of input/output (I/O) terminals on a top surface of the second die and a second set of I/O terminals on a bottom surface of the second die, and wherein the stack of first dies is coupled to the second die through the first set of I/O terminals;
- an interposer, wherein the interposer is coupled to the second die through the second set of I/O terminals;
- and
- a third die positioned aside the second die, wherein the third die is in communication with the second die through the interposer.
A memory die, comprising:
- a substrate;
- multiple sets of first memory cells corresponding to cache sections of the memory die disposed along first and second edges of the substrate, the first and second edges being opposing each other;
- a set of second memory cells corresponding to address sections of the memory die disposed aside a third edge of the substrate and between two of the multiple sets of first memory cells;
- and
- a set of third memory cells corresponding to validity tag sections of the memory die disposed aside a fourth edge of the substrate and between another two of the multiple sets of first memory cells, the third and fourth edges being opposing each other.
A memory circuit, comprising:
- a primary memory circuit in a first die;
- a cache memory circuit in a second die and coupled to the primary memory circuit;
- a memory controller circuit coupled to the primary memory circuit and the cache memory circuit;
- and
- a cache controller circuit coupled to the cache memory circuit and the memory controller circuit, wherein the memory controller circuit and the cache controller circuit are in a third die.
Dependencies are inferred from the claim text.