Storage device for translating address and operating method thereof
AssigneeSK hynix Inc.
InventorsBeom Ju Shin, Yun Jung Yeom
Life of this patent
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Abstract
A memory controller controls an address such that a number of chips included in a memory device can increase. The memory controller includes a flash translation layer configured to translate a logical block address received from a host into a physical block address, wherein the flash translation layer determines an addressing unit of at least one of a plurality of addresses in the physical block address based on a request received from the host and a command controller configured to generate a command representing the addressing unit based on the request.
Claims20
A memory controller comprising:
- a flash translation layer configured to translate a logical block address received from a host into a physical block address, wherein the flash translation layer determines an addressing unit for column addresses included in the physical block address based on a request received from the host;
- and
- a command controller configured to generate a command representing the addressing unit based on the request,
- wherein the column addresses specify column lines of memory cells and are expressed in byte addressing of a 1-byte unit or block addressing of a multi-byte unit,
- wherein the column addresses sequentially increase by 1 byte in the byte addressing or sequentially increase by multiple bytes in the block addressing, and
- wherein the addressing unit indicates whether the column addresses are translated according to the byte addressing or the block addressing.
A memory device, comprising:
- an input/output circuit configured to receive a command and an address;
- a column decoder configured to decode a column address in the address;
- and
- a control logic configured to receive the command and the address from the input/output circuit and control the input/output circuit and the column decoder to perform an operation based on the command and the address, wherein the control logic generates a selection signal based on whether the command represents an addressing unit for the column address,
- wherein the column address specifies a column line of memory cells and is expressed in byte addressing of a 1-byte unit or block addressing of a multi-byte unit,
- wherein the column addresses sequentially increase by 1 byte in the byte addressing or sequentially increase by multiple bytes in the block addressing, and
- wherein the addressing unit indicates whether the column addresses are translated according to the byte addressing or the block addressing.
A storage device, comprising:
- a memory device, and
- a memory controller configured to control the memory device,
- wherein the memory controller translates a logical block address received from a host into a physical block address and outputs the physical block address to the memory device,
- wherein the memory controller determines an addressing unit for column addresses included in the physical block address based on a request from the host, and generates a command representing the addressing unit,
- wherein the memory device generates a selection signal based on the command representing the addressing unit,
- wherein the column addresses specify column lines of memory cells and are expressed in byte addressing of a 1-byte unit or block addressing of a multi-byte unit,
- wherein the column addresses sequentially increase by 1 byte in the byte addressing or sequentially increase by multiple bytes in the block addressing, and
- wherein the addressing unit indicates whether the column addresses are translated according to the byte addressing or the block addressing.
Dependencies are inferred from the claim text.