Method and apparatus for performing access control of memory device with aid of additional physical address information

A memory device, comprising:

• a non-volatile (NV) memory, configured to store information, wherein the NV memory comprises a plurality of NV memory elements;
• and
• a controller, coupled to the NV memory, configured to control operations of the memory device, wherein the controller comprises:
• a processing circuit, configured to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller;
• wherein:
• during a garbage collection procedure, the controller reads valid data from a source block and writes the valid data of the source block into a destination block to be valid data of the destination block, wherein the source block and the destination block represent a first physical block within a first NV memory element of the plurality of NV memory elements and a second physical block within a second NV memory element of the plurality of NV memory elements, respectively;
• the controller updates at least one logical-to-physical (L2P) address mapping table to make the at least one L2P address mapping table comprise both of a first physical address associated with a first logical address and a second physical address associated with the first logical address, wherein the first physical address indicates where the valid data of the source block is stored within the first physical block, and the second physical address indicates where the valid data of the destination block is stored within the second physical block;
• the controller receives a first read request from the host device, wherein the first read request indicates reading at the first logical address, and the first read request comprises a first read command among the plurality of host commands;
• in response to the first read request, the controller reads the valid data of the destination block according to the second physical address associated with the first logical address;
• the controller receives a second read request from the host device, wherein the second read request indicates reading at the first logical address, and the second read request comprises a second read command among the plurality of host commands;
• and
• in response to the second read request, the controller reads the valid data of the source block according to the first physical address associated with the first logical address.

A controller of a memory device, the memory device comprising the controller and a non-volatile (NV) memory, the NV memory comprising a plurality of NV memory elements, the controller comprising:

• a processing circuit, configured to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller;
• wherein:
• during a garbage collection procedure, the controller reads valid data from a source block and writes the valid data of the source block into a destination block to be valid data of the destination block, wherein the source block and the destination block represent a first physical block within a first NV memory element of the plurality of NV memory elements and a second physical block within a second NV memory element of the plurality of NV memory elements, respectively;
• the controller updates at least one logical-to-physical (L2P) address mapping table to make the at least one L2P address mapping table comprise both of a first physical address associated with a first logical address and a second physical address associated with the first logical address, wherein the first physical address indicates where the valid data of the source block is stored within the first physical block, and the second physical address indicates where the valid data of the destination block is stored within the second physical block;
• the controller receives a first read request from the host device, wherein the first read request indicates reading at the first logical address, and the first read request comprises a first read command among the plurality of host commands;
• in response to the first read request, the controller reads the valid data of the destination block according to the second physical address associated with the first logical address;
• the controller receives a second read request from the host device, wherein the second read request indicates reading at the first logical address, and the second read request comprises a second read command among the plurality of host commands;
• and
• in response to the second read request, the controller reads the valid data of the source block according to the first physical address associated with the first logical address.