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US 11,687,443 B2Granted
Tiered persistent memory allocation
AssigneeEMC IP Holding Company LLC
InventorsOwen Martin, Michael Scharland, Earl Medeiros, Parmeshwr Prasad
Life of this patent
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Abstract
The present disclosure relates to one or more memory management techniques. In embodiments, one or more regions of storage class memory (SCM) of a storage array is provisioned as expanded global memory. The one or more regions can correspond to SCM persistent cache memory regions. The storage array's global memory and expanded global memory can be used to execute one or more storage-related services connected to servicing (e.g., executing) an input/output (IO) operation.
Claims16
A method comprising:
- provisioning one or more regions of storage class memory (SCM) of a storage array as expanded global memory, the one or more regions corresponding to SCM persistent cache memory regions;
- configuring at least one translation lookaside buffer (TLB) to map at least a portion of virtual memory addresses to corresponding physical global cache memory addresses;
- updating a virtual memory searchable data structure with a status of each corresponding physical global cache memory address;
- generating the virtual memory searchable data structure configured to present the virtual memory addresses to one or more host devices;
- mapping each virtual memory address to a physical memory address of the global cache memory or the expanded global memory;
- configuring the virtual memory searchable data structure with direct access to the physical global cache memory or the physical expanded global memory;
- and
- executing one or more storage-related services to service an input/output (JO) operation using one or more of the expanded global memory and global cache memory.
5 more elements
An apparatus comprising a memory and at least one processor configured to:
- provision one or more regions of storage class memory (SCM) of a storage array as expanded global memory, the one or more regions correspond to SCM persistent cache memory regions;
- configure at least one translation lookaside buffer (TLB) to map at least a portion of virtual memory addresses to corresponding physical global cache memory addresses;
- update a virtual memory searchable data structure with a status of each corresponding physical global cache memory address;
- generate the virtual memory searchable data structure configured to present the virtual memory addresses to one or more host devices;
- map each virtual memory address to a physical memory address correspond to the global cache memory or the expanded global memory;
- configure the virtual memory searchable data structure with direct access to the physical global cache memory or the physical expanded global memory;
- and
- execute one or more storage-related services to service an input/output (JO) operation using one or more of the expanded global memory and global cache memory.
5 more elements
Dependencies are inferred from the claim text.