Glitch suppression apparatus and method
AssigneeSTMicroelectronics International N.V.
InventorAvneep Kumar Goyal
Life of this patent
Estimating the term…
Abstract
An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.
Claims20
An apparatus comprising:
- a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer;
- a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer;
- and
- a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.
A method comprising:
- placing a first glitch suppression buffer at an end of a first common signal path to suppress glitches of a first signal before the first signal flows into two different signal paths coupled to a main core processor and a shadow core processor, respectively;
- placing a second glitch suppression buffer at an end of a second common signal path to suppress glitches of a second signal before the second signal flows into two different signal paths coupled to the main core processor and the shadow core processor, respectively;
- and
- placing a third glitch suppression buffer at an end of a third common signal path to suppress glitches of a third signal before the third signal flows into two different signal paths coupled to the main core processor and the shadow core processor, respectively.
A system comprising:
- a plurality of glitch suppression buffers configured to suppress a plurality of glitches of a plurality of signals, each of the plurality of glitch suppression buffers being placed at an end of a common path of a corresponding signal before the corresponding signal is routed to two different paths;
- a main core processor configured to receive the plurality of signals through a plurality of main buffers;
- a shadow core processor configured to receive the plurality of signals through a plurality of shadow buffers;
- and
- a fault control unit configured to compare an output signal of the main core processor with an output signal of the shadow core processor, and detect whether the output signal of the main core processor matches the output signal of the shadow core processor.
Dependencies are inferred from the claim text.