Generating a balanced codeword protected by an error correction code
AssigneeMicron Technology, Inc.
InventorChristophe Vincent Antoine Laurent
Life of this patent
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Abstract
Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device may receive data bits for storage. Based on the data bits, the memory device may generate a codeword that includes the data bits, parity bits, and placeholder bits. The memory device may balance the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device may store at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device may re-invert the appropriate packets to recover the original data bits.
Claims20
An apparatus, comprising:
- a decoder comprising a first set of inputs coupled with a memory and a second set of inputs permanently coupled with a reference voltage, the decoder configured to decode a codeword based at least in part on bits sensed from the memory and bits represented by the reference voltage;
- and
- a logic gate coupled with the memory and the decoder, the logic gate configured to invert a bit of the bits sensed from the memory based at least in part on a control signal output by the decoder.
An apparatus, comprising:
- an encoder configured to generate a codeword comprising data bits, parity bits, and placeholder bits;
- a first plurality of logic gates configured to invert a set of bits in the codeword according to an inversion pattern;
- a memory configured to discard the placeholder bits and to store the data bits and the parity bits;
- a decoder configured to:
- reconstruct the codeword using the stored data bits, the stored parity bits, and a set of replacement bits from a reference voltage source in place of the placeholder bits;
- and
- determine the inversion pattern used to invert the set of bits based at least in part on an error in the reconstructed codeword;
- and
- a second plurality of logic gates configured to invert the set of bits in the reconstructed codeword based at least in part on the inversion pattern.
An apparatus, comprising:
- an encoder configured to generate a codeword comprising data bits, parity bits, and placeholder bits;
- a first plurality of logic gates configured to invert a set of bits in the codeword according to an inversion pattern;
- a comparator configured to determine a ratio of logic values for the codeword;
- circuitry configured to add one or more padding bits to the codeword based at least in part on the ratio of logic values;
- and
- a memory configured to store the data bits, the parity bits, and the one or more padding bits.
Dependencies are inferred from the claim text.