Error check and scrub for semiconductor memory device
AssigneeMicron Technology, Inc.
InventorsRandall J. Rooney, Matthew A. Prather
Life of this patent
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Abstract
Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.
Claims20
A memory device comprising:
- a memory array including a bank of memory cells;
- an error-correction code (ECC) circuit coupled with the memory array;
- and
- circuitry coupled with the memory array and the ECC circuit, the circuitry configured to:
- receive, from a host device, a first refresh command directed to the bank of memory cells;
- in response to receiving the first refresh command, retrieving data from a target row of the bank of memory cells, the data comprising a code word corresponding to an address associated with the target row;
- detecting at least one error in the code word using the ECC circuit;
- receiving, at the memory device, a second refresh command directed to the bank of memory cells;
- and
- in response to receiving the second refresh command, writing at the address the code word with the at least one error corrected.
A method comprising:
- receiving, at a memory device, a first refresh command directed to a bank of memory cells;
- retrieving, in response to receiving the first refresh command, data from a target row of the bank, the data comprising a code word corresponding to an address associated with the target row;
- detecting at least one error in the code word of the retrieved data;
- receiving, at the memory device, a second refresh command directed to the bank of memory cells;
- and
- writing at the address, in response to receiving the second refresh command, the code word with the at least one error corrected.
A method comprising:
- receiving, at a memory device, a first refresh command directed to a bank of memory cells that includes a plurality of rows;
- and
- in response to receiving the first refresh command:
- retrieving a first code word from a first row of the plurality of rows, the first code word corresponding to an address associated with the first row;
- and
- checking for one or more errors in the first code word using an error-correction code (ECC) circuit of the memory device.
Dependencies are inferred from the claim text.