Shared error correction code (ECC) circuitry

A method comprising:

• determining, by an error correction code (ECC) engine, a first ECC value based on first data;
• writing the first ECC value to a first memory bank;
• determining, by the ECC engine, a second ECC value based on second data;
• writing the second ECC value to a second memory bank;
• reading third data from the first memory bank;
• determining, by the ECC engine, a third ECC value based on the third data;
• reading fourth data from the second memory bank;
• and
• determining, by the ECC engine, a fourth ECC value based on the fourth data.

An apparatus comprising:

• an interface;
• a first memory bank coupled to the interface;
• a second memory bank coupled to the interface;
• error correction code (ECC) circuitry coupled between the interface and the first and second memory banks, the ECC circuitry configured to:
• provide ECC determinations for the first and second memory banks for read operations and write operations;
• a first data path coupled between the first memory bank and the ECC circuitry;
• and
• a second data path coupled between the second memory bank and the ECC circuitry.

A memory comprising:

• a single die comprising:
• multiple memory banks;
• an interface coupled to the multiple memory banks, the interface configured to be coupled to an interconnect that is external to the single die;
• and
• error correction code (ECC) logic coupled between the interface and the multiple memory banks, the ECC logic configured to provide ECC processing for each memory bank of the multiple memory banks for read operations and write operations.