Centralized SRAM error location detection and recovery mechanism

A data storage device, comprising:

• two or more memory devices;
• and
• a controller coupled to the two or more memory devices, wherein the controller is configured to:
• determine that one or more memory devices of the two or more memory devices needs additional error correction code (ECC), wherein:
• data programmed to the one or more memory devices includes ECC;
• the ECC is single-error-correction double-error-detection (SECDED) code;
• the additional ECC is parity data;
• and
• the additional ECC is generated based on the controller detecting that the programmed data has two errors using the SECDED code;
• and
• program the additional ECC to a first memory device disposed in a central module, wherein the first memory device is distinct from the two or more memory devices, and wherein the two or more memory devices are coupled to the central module.

A data storage device, comprising:

• memory means;
• and
• a controller coupled to the memory means, wherein the controller comprises:
• a first volatile memory, wherein:
• the first volatile memory is distinct from the memory means;
• the first volatile memory is configured to store first error correction code (ECC);
• and
• the first ECC is single-error-correction double-error-detection (SECDED) code;
• and
• a second volatile memory disposed in a central module, wherein:
• the second volatile memory is distinct from the first volatile memory and the memory means;
• the second volatile memory is configured to store second ECC;
• the second ECC is additional ECC for the first volatile memory;
• the additional ECC is parity data;
• and
• the additional ECC is generated based on the controller detecting that data programmed to the memory means has two errors using the SECDED code.