Technologies for hybrid field-programmable gate array application-specific integrated circuit code acceleration

A method comprising:

• performing, by a field-programmable gate array (FPGA) of a computing device, one or more algorithm tasks of an algorithm, wherein the algorithm to perform a service request that is offloaded to the FPGA;
• determining, by the FPGA, a primitive task associated with an algorithm task;
• encapsulating, by the FPGA, the primitive task in a buffer of the FPGA, wherein the buffer is accessible by an application-specific integrated circuit (ASIC) of the computing device;
• and
• returning, by the FPGA, one or more results of the service request responsive to the ASIC performing the primitive task.

A non-transitory computer-readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to:

• performing, by a field-programmable gate array (FPGA) of the computing device, one or more algorithm tasks of an algorithm, wherein the algorithm to perform a service request that is offloaded to the FPGA;
• determining, by the FPGA, a primitive task associated with an algorithm task;
• encapsulating, by the FPGA, the primitive task in a buffer of the FPGA, wherein the buffer is accessible by an application-specific integrated circuit (ASIC) of the computing device;
• and
• returning, by the FPGA, one or more results of the service request responsive to the ASIC performing the primitive task.