Configurable logic platform with reconfigurable processing circuitry
AssigneeThroughPuter, Inc.
InventorMark Henrik Sandstrom
Life of this patent
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Abstract
An architecture for a load-balanced groups of multi-stage manycore processors shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.
Claims17
A system comprising a plurality of hardware-implemented manycore processors, each including an array of Field Programmable Gate Array (FPGA) cores, the plurality of manycore processors connected by a packet switching network, each given manycore processor configured as a local manycore processor to concurrently implement in hardware:
- a plurality of application tasks, including at least one local application task running on the local manycore processor and configured to process input packet data originating from multiple sources, the multiple sources including at least one remote application task hosted on at least one remote manycore processor of the plurality of manycore processors;
- First-In-First-Out (FIFO) packet buffer control hardware logic to control read and write packet data operations, for each of a plurality of FIFO buffers;
- receive hardware logic in communication with the FIFO packet buffer control hardware logic, the receive hardware logic configured to
- inspect each given packet of a plurality of first packets received for delivery to the at least one local application task, the plurality of first packets including one or more packets received from the at least one remote application task, select, based at least in part on source information for each given packet, a corresponding FIFO buffer for each given packet, and
- direct the FIFO packet buffer control hardware logic to write packet data from each given packet to the selected corresponding FIFO buffer for that given packet;
- prioritization hardware logic in communication with the FIFO packet buffer control hardware logic, the prioritization logic configured to
- based at least in part on FIFO buffer fill level data of at least some of the plurality of FIFO buffers, select an order for packet data from the plurality of FIFO buffers to be presented as input packet data to the at least one local application task, and direct the FIFO packet buffer control hardware logic to read and transmit packet data from the plurality of FIFO buffers to the at least one local application task in the selected order;
- and
- send permission hardware logic configured to
- based at least in part on the FIFO buffer fill level data of at least one of the FIFO buffers, determine a respective sending permission for each of the remote manycore processors or each of the remote application tasks, and based at least in part upon changes in the respective sending permissions for each of the remote manycore processors or each of the remote application tasks, cause the local manycore processor to transmit a send permission signal to one or more of the remote manycore processors.
A method of operating a system comprising a plurality of hardware-implemented manycore processors, each including an array of Field Programmable Gate Array (FPGA) cores, the plurality of manycore processors connected by a packet switching network, the method comprising:
- configuring each manycore processor as a local manycore processor to concurrently implement in hardware
- a plurality of application tasks, including at least one local application task running on the local manycore processor and configured to process input packet data originating from multiple sources, the multiple sources including at least one remote application task hosted on at least one remote manycore processor of the plurality of manycore processors, First-In-First-Out (FIFO) packet buffer control hardware logic to control read and write packet data operations, for each of a plurality of FIFO buffers, receive hardware logic, prioritization hardware logic, and send permission hardware logic;
- by the receive hardware logic on each respective local manycore processor,
- inspecting each given packet of a plurality of first packets received for delivery to the at least one local application task, the plurality of first packets including one or more packets received from the at least one remote application task, selecting, based at least in part on source information for each given packet, a corresponding FIFO buffer for each given packet, and
- directing the FIFO packet buffer control hardware logic to write packet data from each given packet to the selected corresponding FIFO buffer for that given packet;
- by the prioritization hardware logic on each respective local manycore processor,
- based at least in part on FIFO buffer fill level data of at least one of the plurality of FIFO buffers, selecting an order for packet data from the plurality of FIFO buffers to be presented as input packet data to the at least one local application task, and
- directing the FIFO packet buffer control hardware logic to read and transmit packet data from the plurality of FIFO buffers to the at least one local application task in the selected order;
- and
- by the send permission hardware logic on each respective local manycore processor,
- based at least in part on the FIFO buffer fill level data of at least some of the plurality of FIFO buffers, determining a respective sending permission for each of the remote manycore processors or each of the remote application tasks, and based at least in part upon changes in the respective sending permissions for each of the remote manycore processors or each of the remote application tasks, causing the respective local manycore processor to transmit a send permission signal to one or more of the remote manycore processors.
Dependencies are inferred from the claim text.