Methods and apparatus for cache-aware task scheduling in a symmetric multi-processing (SMP) environment

An apparatus for cache-aware task scheduling in a multi-processing environment comprising:

• a cache memory;
• and
• a multi-core processor comprising a source processing core and at least one destination processing core,
• wherein the source processing core is configured to add a first activity stored in a first list of the apparatus to a second list of the apparatus associated with a scheduler of the destination processing core, based on a priority of the first activity,
• wherein the source processing core is configured to determine a resource of the first activity and transmit information indicating the resource to the second list using an interrupt, if the destination processing core is currently executing a second activity having a lower priority than the first activity and working in an interrupt enabled/disabled mode, and
• wherein the destination processing core accesses the information in the second list and executes the first activity based on the information accessed from the second list in response to receipt of the interrupt and otherwise continues the executing of the second activity.