Microprocessor and method for speculatively issuing load/store instruction with non-deterministic access time using scoreboard

A microprocessor, comprising:

• a register file, comprising a plurality of registers;
• a scoreboard, comprising a plurality of scoreboard entries, wherein each scoreboard entry corresponds to one of the registers and comprises respective scoreboard information related to the corresponding register, wherein a first scoreboard entry corresponding to a first register includes first scoreboard information related to a first instruction issued and scheduled to access the first register;
• a decode/issue unit, issuing a second instruction accessing the first register scheduled to be accessed by the first instruction in which the first scoreboard information of the first scoreboard entry is attached with the second instruction;
• a load/store queue, receiving the second instruction and the first scoreboard information of the first register from the decode/issue unit and resolving a data dependency based on the first scoreboard information of the first register;
• and
• a load/store unit, receiving and executing the second instruction issued from the load/store queue,
• wherein the first scoreboard information of the first scoreboard entry corresponding to the first register records an unknown value representing whether the first instruction has unknown access time for accessing the first register,
• wherein the load/store queue includes a tag execution queue and a data execution queue,
• wherein the second instruction is issued as a plurality of micro-ops including a first micro-op and a second micro-op, the first micro-op is dispatched to the tag execution queue to calculate a memory address and accesses a tag array of a data cache, and the second micro-op is dispatched to the data execution queue to access a data array of the data cache,
• wherein the tag execution queue is independent from the data execution queue, and the data execution queue utilizes a cache hit or miss from the first micro-op in the tag execution queue to access the data array of the data cache.