Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers

A field programmable gate array (FPGA) comprising:

• a processor, comprising:
• a first memory implemented using a plurality of multi-input lookup-tables (LUTs) in the FPGA;
• an instruction cache configured to receive instructions fetched from a second memory, a given instruction of the received instructions comprising first and second instruction identifiers encoded in the given instruction, the first instruction identifier indicating the given instruction's relative position within a group of instructions in the second memory, and the second instruction identifier designating a target instruction other than the given instruction, to receive a result generated by executing the given instruction;
• and
• an instruction scheduler configured to store ready state data in the first memory indexed by an instruction identifier of a corresponding instruction, the stored ready state data indicating state of the corresponding instruction's predicate operands and/or data operands, the instruction scheduler being further configured to issue the corresponding instruction when the stored ready state data indicates that all operand dependencies for the corresponding instruction are satisfied.