Way predictor and enable logic for instruction tightly-coupled memory and instruction cache

A method for predicting between memory structures, the method comprising:

• maintaining a location state indicator which indicates whether a location state for fetching instructions is known or unknown;
• predicting which of the iTIM or the iCache and a particular way to fetch an instruction from based on the location state indicator and a program counter value;
• enabling the predicted iTIM or the predicted iCache and the particular way for a known location state;
• enabling both the iTIM and all N ways of the iCache for parallel access for an unknown location state;
• and,
• updating the location state indicator and the program counter value to predict a next location state for a next instruction;
• and
• returning an instruction via the enabled iTIM, the enabled iCache and the particular way, or the enabled iCache and all N ways.

A processor, comprising:

• an instruction tightly-coupled memory (iTIM);
• an instruction cache (iCache) with N ways, wherein N is at least one;
• a location state indicator configured to indicate whether a location state for fetching instructions is known or unknown;
• and
• an enable circuit configured to:
• enable one of the iTIM or the iCache and a particular way based on the location state indicator and a program counter value when the location state indicator indicates that the location state is known;
• and
• enable both the iTIM and all N ways of the iCache when the location state indicator indicates that the location state is unknown,
• wherein the processor is configured to fetch the instruction via the enabled iTIM, the enabled iCache and the particular way, or the enabled iCache and all N ways.