Multi-variate strided read operations for accessing matrix operands

At least one non-transitory machine accessible storage medium having instructions stored thereon, wherein the instructions, when executed on a machine, cause the machine to:

• receive a first instruction to be executed by a matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on a matrix operand, wherein the first instruction comprises an opcode and an operand identifier, wherein the opcode is to identify the first operation, and wherein the operand identifier is to identify:
• a starting memory address of the matrix operand, wherein the matrix operand is stored out of order in a memory of the matrix processor;
• and
• a strided read sequence associated with the matrix operand, wherein the strided read sequence is stored in the memory, and wherein the strided read sequence indicates a sequence of read operations to read the matrix operand in a correct order from the memory;
• access the strided read sequence stored in the memory;
• read, from the memory, the matrix operand, wherein the matrix operand is read from the memory based on the starting memory address and the strided read sequence;
• and
• cause the first instruction to be executed by the matrix processor, wherein the first instruction is to be executed by performing the first operation on the matrix operand.

A method, comprising:

• receiving a first instruction to be executed by a matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on a matrix operand, wherein the first instruction comprises an opcode and an operand identifier, wherein the opcode is to identify the first operation, and wherein the operand identifier is to identify:
• a starting memory address of the matrix operand, wherein the matrix operand is stored out of order in a memory of the matrix processor;
• and
• a strided read sequence associated with the matrix operand, wherein the strided read sequence is stored in the memory, and wherein the strided read sequence indicates a sequence of read operations to read the matrix operand in a correct order from the memory;
• accessing the strided read sequence stored in the memory;
• reading, from the memory, the matrix operand, wherein the matrix operand is read from the memory based on the starting memory address and the strided read sequence;
• and
• causing the first instruction to be executed by the matrix processor, wherein the first instruction is to be executed by performing the first operation on the matrix operand.

A system, comprising:

• a host processor;
• a memory to store a matrix operand and a strided read sequence, wherein:
• the matrix operand is stored out of order in the memory;
• and
• the strided read sequence indicates a sequence of read operations to read the matrix operand in a correct order from the memory;
• and
• a matrix processor, comprising:
• control circuitry to receive, from the host processor, a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand, wherein the first instruction comprises an opcode and an operand identifier, wherein the opcode is to identify the first operation, and wherein the operand identifier is to identify a starting memory address of the matrix operand and the strided read sequence;
• read circuitry to, based on receiving the first instruction:
• read, from the memory, the strided read sequence identified by the operand identifier;
• and
• read, from the memory, the matrix operand, wherein the matrix operand is read from the memory based on the starting memory address and the strided read sequence identified by the operand identifier;
• and
• execution circuitry to execute the first instruction by performing the first operation on the matrix operand.