Processor overriding of a false load-hit-store detection

A computer system comprising one or more processors and one or more computer-readable memories, wherein a first processor of the one or more processors comprises a processor core configured to perform a method comprising:

• receiving a rejected first load instruction, wherein the rejected first load instruction has been rejected due to a false load-hit-store detection against a first store instruction;
• generating a warning label in response to receiving the false load-hit-store detection;
• adding the warning label to the received first load instruction to create a labeled first load instruction;
• and
• issuing the labeled first load instruction such that the warning label causes the labeled first load instruction to bypass the first store instruction in a store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction.

A processor core comprising one or more hardware facilities comprising at least one execution unit for executing instructions, wherein the processor core is capable of performing a method comprising:

• receiving a rejected first load instruction, wherein the rejected first load instruction has been rejected due to a false load-hit-store detection against a first store instruction;
• generating a warning label in response to receiving the false load-hit-store detection;
• adding the warning label to the received first load instruction to create a labeled first load instruction;
• and
• issuing the labeled first load instruction such that the warning label causes the labeled first load instruction to bypass the first store instruction in a store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction.