Generating memory array control signals
AssigneeMicron Technology, Inc.
InventorHiroshi Akamatsu
Life of this patent
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Abstract
Methods, systems, and devices for generating memory array control signals are described. A timing component may be configured to generate signals for operating a memory array. The timing component may include first logic that indicates when input signals are different, second logic that indicates when at least one of the input signals has a particular state, and third logic that indicates when the input signals have the same state. The output of the second logic and third logic may be controllable by other input signals. An output of the timing component may be set by one of the input signals and reset by the other input signals using the first logic, second logic, and third logic.
Claims20
An apparatus, comprising:
- a signal driver comprising:
- a first driver comprising combinational logic configured to obtain a first control signal based at least in part on a first delay signal and a second delay signal, wherein first logic of the combinational logic is configured to indicate when the first delay signal and the second delay signal have different states, second logic of the combinational logic is configured to indicate when at least one of the first delay signal or the second delay signal have a first state, and third logic of the combinational logic is configured to indicate when the first delay signal and the second delay signal have a same state;
- a second driver configured to obtain a second control signal based at least in part on a third delay signal and a fourth delay signal;
- and
- output logic coupled with the first driver and the second driver and configured to combine the first control signal and the second control signal to obtain a signal for operating a memory array.
An apparatus, comprising:
- first logic, wherein a first input of the first logic is coupled with an exclusive OR gate of the first logic and a first inverter of the first logic, and wherein a second input of the first logic is coupled with the exclusive OR gate of the first logic and a second inverter of the first logic;
- second logic, wherein a first input of the second logic is coupled with an AND gate of the second logic, wherein a second input of the second logic is coupled with the AND gate of the second logic, and wherein a third input of the second logic is coupled with an inverter of the second logic and an inverted OR gate of the second logic;
- and
- third logic, wherein a first input of the third logic is coupled with an AND gate of the third logic and the exclusive OR gate of the first logic, wherein a second input of the third logic is coupled with the AND gate of the third logic and the inverted OR gate of the second logic, and wherein a third input of the third logic is coupled with the AND gate of the third logic and the inverter of the second logic.
An apparatus, comprising:
- a first driver comprising first combinational logic configured to generate a first signal for operating a memory array based at least in part on a first delay signal and a second delay signal, wherein first logic of the first combinational logic is configured to indicate when the first delay signal and the second delay signal have different states, second logic of the first combinational logic is configured to indicate when at least one of the first delay signal or the second delay signal have a first state, and third logic of the first combinational logic is configured to indicate when the first delay signal and the second delay signal have a same state;
- a second driver comprising second combinational logic configured to generate a second signal for operating the memory array based at least in part on a third delay signal and a fourth delay signal;
- and
- a composite driver configured to generate a third signal for operating the memory array based at least in part on a fifth delay signal and a sixth delay signal, the composite driver including a third driver comprising third combinational logic that has a same configuration as the first combinational logic and a fourth driver comprising fourth combinational logic that has a same configuration as the second combinational logic.
Dependencies are inferred from the claim text.