Time to live for load commands
AssigneeMicron Technology, Inc.
InventorsShivasankar Gunasekaran, Samuel E. Bradshaw, Justin M. Eno, Ameen D. Akel
Life of this patent
Estimating the term…
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AssigneeMicron Technology, Inc.
InventorsShivasankar Gunasekaran, Samuel E. Bradshaw, Justin M. Eno, Ameen D. Akel
Estimating the term…
A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory sub-system can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.
An apparatus, comprising:
A method, comprising:
A non-transitory computer storage medium storing instructions which, when executed in an apparatus having a plurality of memory devices with different latencies in accessing data stored in the memory devices, cause the apparatus to perform a method, the method comprising:
Dependencies are inferred from the claim text.