DRAM command streak efficiency management
AssigneeAdvanced Micro Devices, Inc.
InventorsGuanhao Shen, Ravindra Nath Bhargava
Life of this patent
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Abstract
A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a different type based on a first set of one or more conditions indicating intra-burst efficiency.
Claims20
A memory controller, comprising:
- a command queue having a first input for receiving memory access requests;
- and
- an arbiter coupled to the command queue for selecting entries from the command queue, and causing them to be transmitted over a memory channel, the arbiter operable to:
- transmit streaks of consecutive read commands and streaks of consecutive write commands over the memory channel;
- transmit a current streak of one of consecutive read commands or consecutive write commands for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter;
- and
- following the minimum burst length, based on whether no commands for a new streak are available for which a column-address-strobe (CAS) command can be sent within a first defined CAS-to-CAS interval, continue the current streak.
A method, comprising:
- causing streaks of consecutive read commands and streaks of consecutive write commands to be transmitted over a memory channel;
- transmitting a current streak of one of consecutive read commands or consecutive write commands for at least a minimum burst length based on a number of commands of a designated type available to be selected by an arbiter;
- and
- following the minimum burst length, based on whether no commands for a new streak are available for which a column-address-strobe (CAS) command can be sent within a first defined CAS-to-CAS interval, continuing the current streak.
A data processing system, comprising:
- a processing unit;
- a data fabric coupled to the processing unit;
- and
- a memory controller coupled to the data fabric for fulfilling memory requests from the processing unit, the memory controller comprising:
- a command queue having a first input for receiving memory access requests;
- an arbiter coupled to the command queue for selecting entries from the command queue, and causing them to be transmitted over a memory channel to at least one dynamic random access memory, the arbiter operable to:
- transmit streaks of consecutive read commands and streaks of consecutive write commands over the memory channel;
- transmit a current streak of one of consecutive read commands or consecutive write commands for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter;
- and
- following the minimum burst length, based on whether no commands for a new streak are available for which a column-address-strobe (CAS) command can be sent within a first defined CAS-to-CAS interval, continue the current streak.
Dependencies are inferred from the claim text.