Latency and throughput centric reconfigurable storage device
AssigneeSamsung Electronics Co., Ltd.
InventorPankaj Mehra
Life of this patent
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Abstract
A storage device includes: a storage controller to receive data from a host device, and to store the data in storage memory; and a reconfigurable integrated circuit communicably connected to the storage controller, and to accelerate logic operations executed on the data stored in the storage memory, the reconfigurable integrated circuit including: a first logic block to execute a static logic operation from among the logic operations; a second logic block to execute one or more dynamic logic operations from among the logic operations; and a plurality of memory buffers configured to store inputs and outputs of the first and second logic blocks.
Claims20
A storage device comprising:
- a storage controller configured to receive data from a host device, and to store the data in storage memory;
- and
- a reconfigurable integrated circuit communicably connected to the storage controller, and configured to accelerate logic operations executed on the data stored in the storage memory, the reconfigurable integrated circuit comprising:
- a first logic block configured to execute a static logic operation from among the logic operations corresponding to a first pipeline workflow;
- a second logic block configured to execute one or more dynamic logic operations from among the logic operations corresponding to the first pipeline workflow;
- and
- a plurality of memory buffers configured to store inputs and outputs of the first and second logic blocks,
- wherein the static logic operation is an operation from among the logic operations of the first pipeline workflow having a completion time less than a reconfiguration time of the second logic block, and the first logic block is configured to be reconfigured to execute a different logic operation for a second pipeline workflow, and
- wherein the second logic block is configured to be reconfigured to execute different ones of the one or more dynamic logic operations for different stages of the first pipeline workflow based on an amount of resources consumed by the different ones of the one or more dynamic logic operations and available resources allocated for the second logic block in the different stages.
A method for accelerating operations in a storage device comprising a storage controller, storage memory, and a reconfigurable integrated circuit comprising a first logic block, a second logic block, and a buffer, the method comprising:
- executing, by the first logic block, a first logic operation on input data stored in the storage memory;
- storing, by the first logic block, outputs of the first logic operation in an intermediate output buffer of the buffer;
- configuring, by the reconfigurable integrated circuit, a second logic operation in the second logic block;
- designating, by the reconfigurable integrated circuit, the intermediate output buffer as an input buffer for the second logic operation;
- designating, by the reconfigurable integrated circuit, an input buffer of the first logic operation as an output buffer for the second logic operation;
- and
- executing, by the second logic block, the second logic operation on the outputs of the first logic operation stored in the intermediate output buffer,
- wherein the first logic operation is an operation having a completion time less than a reconfiguration time of the second logic block, and the first logic block is configured to be reconfigured to execute different logic operations for different pipeline workflows.
A method for accelerating operations in a storage device comprising a storage controller, storage memory, and a reconfigurable integrated circuit comprising a first logic block, a second logic block, and a buffer, the method comprising:
- executing, by the first logic block, a first logic operation on input data stored in the storage memory;
- storing, by the first logic block, outputs of the first logic operation in an intermediate output buffer of the buffer;
- configuring, by the reconfigurable integrated circuit, a second logic operation in the second logic block;
- designating, by the reconfigurable integrated circuit, the intermediate output buffer as an input buffer for the second logic operation;
- and
- executing, by the second logic block, the second logic operation on the outputs of the first logic operation stored in the intermediate output buffer,
- wherein the designating of the intermediate output buffer as the input buffer for the second logic operation comprises:
- determining whether the first logic operation is suspended;
- designating the intermediate output buffer as the input buffer for the second logic operation in response to determining that the first logic operation is suspended;
- and
- designating an input buffer of the first logic operation as an output buffer for the second logic operation.
Dependencies are inferred from the claim text.