Memory controller for managing data and error information

A method, comprising:

• receiving first signals indicative of data from a memory device by a plurality of data pins of a memory interface of a memory controller configured for a low-power double data rate (LPDDRx) protocol, wherein the data comprises encrypted data;
• receiving second signals indicative of error detection information and error correction information from the memory device by a plurality of data mask inversion (DMI) pins of the memory interface of the memory controller configured for LPDDRx protocol contemporaneous with the receipt of the data;
• performing an error correction operation on the data based on the error correction information;
• decrypting the data after performing the error correction operation;
• performing an error detection operation on the data, after decrypting the data, based on the error detection information;
• and
• transmitting third signals indicative of the data to a host by interface management circuitry of the memory controller configured for a compute express link (CXL) protocol.

A memory controller, comprising:

• interface management circuitry configured for a compute express link (CXL) protocol;
• data management circuitry coupled to the interface management circuitry, wherein the data management circuitry includes:
• error detection circuitry configured to perform error detection operations on data;
• and
• error correction circuitry coupled to the error detection circuitry and configured to perform error correction operations on the data;
• media control circuitry coupled to the data management circuitry;
• and
• a memory interface, configured for a low-power double data rate (LPDDRx) protocol, coupled to the media control circuitry, wherein the memory interface includes a plurality of physical memory interfaces, each physical memory interface including a respective plurality of data pins and a respective plurality of data mask inversion (DMI) pins;
• wherein the media control circuitry is configured to:
• exchange first signals indicative of the data via the respective plurality of data pins;
• and
• exchange second signals indicative of error correction information and error detection information via the respective plurality of DMI pins contemporaneously with the exchange of the data;
• and
• wherein the data management circuitry is configured to selectively enable the error correction circuitry based on a type of memory being operated.

A memory system, comprising:

• a plurality of memory devices each including at least one memory array;
• and
• a memory controller coupled to the plurality of memory devices, wherein the memory controller includes:
• interface management circuitry configured for a compute express link (CXL) protocol and configured to be coupled to a host via an interface configured for a peripheral component interconnect express (PCIe) protocol;
• data management circuitry coupled to the interface management circuitry, wherein the data management circuitry includes at least one of:
• error detection circuitry configured to perform error detection operations on data;
• and
• error correction circuitry coupled to the error detection circuitry and configured to perform error correction operations on the data;
• and
• media control circuitry coupled to the data management circuitry;
• and
• a respective physical interface with each of the plurality of memory devices, each physical interface including a respective plurality of data pins and a respective plurality of data mask inversion (DMI) pins;
• wherein the media control circuitry is configured to:
• operate a first subset of the plurality of memory devices according to a first protocol and a second subset of the plurality of memory devices according to a second protocol;
• disable at least one low-power feature with respect to the first subset of memory devices;
• enable the at least one low-power feature with respect to the second subset of memory devices;
• exchange first signals indicative of the data with a respective memory device via the respective plurality of data pins;
• and
• exchange second signals indicative of at least one of error correction information and error detection information with the respective memory device via the respective plurality of DMI pins contemporaneously with the exchange of the data.

A method, comprising:

• receiving a first signal indicative of data from a host by interface management circuitry of a memory controller configured for a Compute Express Link (CXL) protocol;
• generating error detection information based on the data by data management circuitry of the memory controller;
• generating error correction information based on the data by the data management circuitry;
• transmitting a second signal indicative of the data to a memory device by a plurality of data pins of a memory interface of the memory controller configured for a low-power double data rate (LPDDRx) protocol;
• transmitting a third signal indicative of the error detection information and the error correction information to the memory device by a plurality of data mask inversion (DMI) pins of the memory interface of the memory controller configured for LPDDRx protocol contemporaneous with the transmission of the data;
• and
• prohibiting, by firmware, enablement of a sub-threshold current reduce circuit (SCRC) of the memory device.