Elastic buffer based asymmetric pipeline FIFO process
AssigneeWestern Digital Technologies, Inc.
InventorsYevgeny Lazarev, Elkana Richter, Shay Benisty
Life of this patent
Estimating the term…
Abstract
The present disclosure generally relates to efficient management of an elastic buffer. Efficient management can be achieved by using an asymmetric asynchronous First In, First Out (FIFO) approach based on normalization of write and read pointers. The normalization is done in accordance with the FIFO depth while keeping a single bit change approach. In order to achieve an asymmetric dynamic ability for part per million (PPM) compensation, a plurality of sub-FIFOs are used for opponent side pointer synchronization. Combining the features allows for creating an asynchronous asymmetric FIFO with pipeline characteristics.
Claims14
A data storage device, comprising:
- one or more memory devices;
- and
- a controller coupled to the one or more memory devices, wherein:
- the controller is configured to deliver data to a host device according to an asynchronous asymmetric First In, First Out (FIFO) process;
- the asynchronous asymmetric FIFO process comprises calculating a minimum index value and a maximum index value;
- and
- the minimum index value is a lower bound of a memory depth range and the maximum index value is an upper bound of the memory depth range.
A data storage device, comprising:
- one or more memory devices;
- and
- a controller coupled to the one or more memory devices, wherein the controller is configured to deliver data to a host device according to an asynchronous asymmetric First In, First Out (FIFO) process, wherein:
- the asynchronous asymmetric FIFO process comprises calculating a minimum index value and a maximum index value;
- and
- the minimum index value is calculated according to the following formula:
- ((required depth rounded to the power of 2)/2)−((required depth)/2)
- wherein the required depth is a number of index entries times two to account for full and empty status, and where rounded to the power of 2 is an even number of a geometric sequence starting at 2 with a common ratio of 2.
A data storage device, comprising:
- one or more memory devices;
- and
- a controller coupled to the one or more memory devices, wherein the controller comprises:
- a main First In, First Out (FIFO) chip;
- a write FIFO chip coupled to the main FIFO chip;
- a read FIFO chip coupled to the main FIFO chip;
- a write sub-FIFO chip array, wherein the write sub-FIFO chip array is coupled to the write FIFO chip and the read FIFO chip;
- and
- a read sub-FIFO chip array, wherein the read sub-FIFO chip array is coupled to the write FIFO chip and the read FIFO chip;
- wherein:
- the write FIFO chip is capable of sending signals to the main FIFO chip and the read sub-FIFO chip array concurrently;
- the read FIFO chip is capable of sending signals to the main FIFO chip and the write sub-FIFO chip array concurrently;
- the read FIFO chip is configured to send a read address to the main FIFO chip;
- the read FIFO chip is configured to send a read pointer to the write sub-FIFO chip array;
- and
- the write sub-FIFO chip array is configured to deliver a write double clock read pointer to the write FIFO chip.
Dependencies are inferred from the claim text.