Memory device status push within memory sub-system
AssigneeMicron Technology, Inc.
InventorsChulbum Kim, Sundararajan Sankaranarayanan
Life of this patent
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Abstract
A local media controller of a first memory device receives a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device. The local media controller initializes a counter associated with the first memory device. Responsive to determining that the value of the counter matches the first number of cycles, the local media controller transmits a status of the first memory device via the bus. Furthermore, responsive to determining that the status is ready, the local media controller sends, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.
Claims20
A method comprising:
- receiving, by a local media controller of a first memory device, a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device;
- initializing a counter associated with the first memory device;
- responsive to determining that a value of the counter matches the first number of cycles, transmitting a status of the first memory device via the bus, wherein the status comprises a second number of cycles associated with the first memory device, wherein the second number of cycles is determined in view of the status of the first memory device;
- and
- responsive to determining that the status of the first memory device is ready, sending, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- receiving, by a local media controller of a first memory device, a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device;
- initializing a counter associated with the first memory device;
- responsive to determining that a value of the counter matches the first number of cycles, transmitting a status of the first memory device via the bus, wherein the status comprises a second number of cycles associated with the first memory device, wherein the second number of cycles is determined in view of the status of the first memory device;
- and
- responsive to determining that the status of the first memory device is ready, sending, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.
A system comprising:
- a plurality of memory devices;
- and
- a processing device, operatively coupled to the plurality of memory devices, to perform operations comprising:
- receiving, by a local media controller of a first memory device of the plurality of memory devices, a first number of cycles broadcasted by a second memory device of the plurality of memory devices via a bus connecting the first memory device and the second memory device;
- initializing a counter associated with the first memory device;
- responsive to determining that a value of the counter matches the first number of cycles, transmitting a status of the first memory device via the bus, wherein the status comprises a second number of cycles associated with the first memory device, wherein the second number of cycles is determined in view of the status of the first memory device;
- and
- responsive to determining that the status of the first memory device is ready, sending, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.
Dependencies are inferred from the claim text.