US 11,687,148 B1Granted

Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS

AssigneeInternational Business Machines Corporation

InventorsRobert K. Montoye, Kevin Tien, Yutaka Nakamura, Jeffrey Haskell Derby, Martin Cochet, Todd Edward Takken, Xin Zhang

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Abstract

A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.

Claims20

Dependent claims

A system for dynamic voltage and frequency scaling of operating processing cores, the system comprising:

a stacked circuit configuration including at least two or more processor core devices, each processor core device having a first terminal for connection to a first voltage rail conductor and having a second terminal connection for connection to a second lower voltage rail conductor, each said processor core device comprising a state monitor unit for monitoring a functional state of said processor core device;
a current provision network comprising first tunable current supplying devices interconnecting first terminals of a plurality of said at least two or more processor core devices to the first voltage rail conductor and second tunable current supplying devices interconnecting the second terminals of a plurality of said at least two or more processor core devices to the second lower voltage rail conductor, and a plurality of tunable bridge current supplying devices interconnecting a first terminal of each of a respective subset of processor core devices to a second terminal of each of a plurality of other processor core devices of said subset;
and
a control unit including a processor for receiving real-time functional state monitor signals issuing from said state monitor unit of said processor core devices and issuing one or more control signals and for adjusting a resistance of one or more said first tunable current supplying devices, said second tunable current supplying devices or said tunable bridge current supplying devices to thereby adjust a voltage across a processor core device to achieve a target frequency of operation at said processor core in response to the received real-time state monitor signals.

1 more element

A method for dynamic voltage and frequency scaling of operating processing cores, the method comprising:

configuring one or more stacked processor core units, each stacked processor core unit comprising:
a lower processor core device having a first terminal connected to a first voltage rail conductor through a first tunable current supplying device and a second terminal connected directly to a second lower voltage rail conductor,
one or more upper processor core devices, each upper core device having a first terminal directly connected to said first voltage rail conductor and a second terminal connected to said second lower voltage rail conductor through a second tunable current supplying device, wherein the upper processor core device and lower processor core device each comprises a state monitor unit for monitoring a functional state of that processor core device and generating corresponding feedback signals;
and
a respective tunable bridge current supplying device interconnecting the first terminal of said lower processor core device to the second terminal of each respective one or more upper processor core devices;
and
controlling, using a control processor, based on said feedback signals obtained from each said state monitor unit of a lower processor core device or upper processor core device, a resistance value of one or more said first tunable current supplying device, said second tunable current supplying device and said tunable bridge current supplying device to ensure stable functional operation of said lower or upper processor core devices to achieve a target voltage or frequency of said respective lower or upper processor core.

4 more elements

A method for dynamically controlling stacked processor core network including multiple operating processor core devices, the method comprising:

configuring a resistance value of a first tunable current supplying device connecting a higher voltage terminal of a lower processor core device to a first voltage rail conductor, a lower voltage terminal of said lower processor core device connected directly to a second lower voltage rail conductor;
configuring a resistance value of each of multiple second tunable current supplying devices, each respective second tunable current supplying device connecting a lower voltage terminal of a respective said upper core device of multiple second processor core devices to the second lower voltage rail conductor, a higher voltage terminal of each respective said upper core device of multiple upper processor core devices connected directly to the first voltage rail conductor;
configuring a resistance value of each of multiple tunable bridge current supplying devices, each respective tunable bridge current supplying device interconnecting the lower voltage terminal of each respective multiple upper processor core device to the higher voltage terminal of said lower processor core device, wherein each upper processor core device and lower processor core device comprises a state monitor unit for monitoring a timing margin state of that respective upper processor core or lower processor core device and generating a corresponding feedback signal;
detecting, using a functional state monitor device at each said operating processor core device currently paired to one or more other processor core devices, when a functional timing margin state condition changes at said operating processor core device;
generating, by said respective functional state monitor device, a feedback signal when the timing margin state condition changes at said operating processor core device;
and
tuning, using a control processor, based on the generated feedback signal, the resistance value of one or more said first tunable current supplying device, said second tunable current supplying device or one or more respective said tunable bridge current supplying devices to achieve an optimal timing margin at said operating processor core device and respective currently paired one or more other processor core devices.

4 more elements

Dependencies are inferred from the claim text.