Interface circuit for controlling output impedance of a transmission circuit and an image sensor including ihe same

An interface circuit including a first transmission circuit for transmitting a differential signal to a transmission line via first transfer pads, the interface circuit comprising:

• transmitters configured to output the differential signal;
• a first termination resistor block included in the first transmission circuit and connected between the first transfer pads;
• and
• a second termination resistor block included in a second transmission circuit and connected between second transfer pads,
• wherein, during a first time period, the first transmission circuit is enabled to transmit data and output the differential signal in a first mode, and during the first time period, the second transmission circuit has a high output impedance, the second termination resistor block detects the differential signal and in response to the differential signal connects a second unit resistor between the second transfer pads such that during a second time period after the first time period, the output impedance of the second transmission circuit has a designated impedance,
• wherein, during the second time period, the first transmission circuit outputs data in a second mode, and the second termination resistor block performs impedance matching on the data output from the first transmission circuit, and
• wherein the first mode is a mode in which less power is consumed compared to the second mode, and the second mode is a mode in which data is transmitted at a faster speed compared to the first mode.

An interface circuit including a first transmission circuit for transmitting a signal to a transmission line via transfer pads and a second transmission circuit connected to the transmission line, the interface circuit comprising:

• transmitters configured to output the signal;
• and
• a termination resistor block connected between the transfer pads,
• wherein, when the second transmission circuit connected to the transmission line is in a first mode and is enabled to transmit data in a first time period, an output impedance of a first transmission circuit has a high impedance, and during a second time period after the first time period, the termination resistor block detects a signal sequence output via the second transmission circuit and in response to the detected signal sequence connects a unit resistor between the transfer pads, such that during the second time period an output impedance of the second transmission circuit has a designated impedance different from the high impedance,
• wherein, during the second time period, the first transmission circuit outputs data in a second mode, and the termination resistor block performs impedance matching on the data output from the first transmission circuit, and
• wherein the first mode is a mode in which less power is consumed compared to the second mode, and the second mode is a mode in which data is transmitted at a faster speed compared to the first mode.