Multi-level CPU high current protection

A method comprising:

• storing permission information corresponding to micro architectural events and data types for at least one computational element;
• and
• determining a first permission for the at least one computational element based on the stored permission information;
• and
• determining a second permission for the at least one computational element based on the stored permission information, wherein the at least one computational element is adjusted based on the determined first permission or the determined second permission, wherein at least one of the micro architectural events corresponds to a vector operation to be performed on a vector workload based at least in part on the first determined permission, where at least a second micro architectural event from the micro architectural events is to correspond to an accelerator hardware operation to be performed on an accelerator hardware workload based at least in part on the second determined permission, wherein different micro architectural events for the at least one computational block are assigned different permission types.

A system comprising:

• a processor having a plurality of processor cores;
• memory to store permission information corresponding to micro architectural events and data types for the plurality of processor cores;
• and
• logic circuitry to determine a first permission for a first processor core of the plurality of processor cores and to determine a second permission for the first processor core of the plurality of processor cores based on the stored permission information, wherein the logic circuitry is to adjust the first processor core based on the determined first permission or the determined second permission, wherein at least one of the micro architectural events is to correspond to a vector operation to be performed on a vector workload based at least in part on the determined first permission, where at least a second micro architectural event from the micro architectural events is to correspond to an accelerator hardware operation to be performed on an accelerator hardware workload based at least in part on the determined second permission, wherein different micro architectural events for the plurality of processor cores are to be assigned different permission types.