System and method to manage power throttling
AssigneeMarvell Asia Pte Ltd
InventorsAvinash Sodani, Srinivas Sripada, Ramacharan Sundararaman, Chia-Hsin Chen, Nikhil Jayakumar
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Abstract
A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.
Claims27
A power throttling engine comprising:
- a decoder configured to generate a control signal based on a value of a power throttling signal, wherein the value of the power throttling signal is an amount of power throttling of a device;
- and
- a clock gating logic configured to receive the control signal and further configured to receive a clocking signal, and wherein the clock gating logic is configured to remove clock edges of the clocking signal by generating a throttled clocking signal based on the control signal.
A power throttling engine comprising:
- a component configured to receive a power throttling signal and a thermal sensed signal and to select one of the power throttling signal or the thermal sensed signal;
- a decoder configured to generate a control signal based on a value of the selected signal, wherein the value of the selected signal is an amount of power throttling of a device;
- and
- a clock gating logic configured to receive the control signal and further configured to receive a clocking signal, and wherein the clock gating logic is configured to remove clock edges of the clocking signal by generating a throttled clocking signal based on the control signal.
A method comprising:
- receiving a power throttling signal;
- receiving a thermal sensed signal;
- selecting one of the power throttling signal or the thermal sensed signal;
- generating a control signal based on a value of the selected signal, wherein the value of the selected signal is an amount of power throttling of a device;
- and
- removing clock edges of a clocking signal based on the control signal to generate a throttled clocking signal.
A system comprising:
- a means for receiving a power throttling signal;
- a means for receiving a thermal sensed signal;
- a means for selecting one of the power throttling signal or the thermal sensed signal;
- a means for generating a control signal based on a value of the selected signal, wherein the value of the selected signal is an amount of power throttling of a device;
- and
- a means for removing clock edges of a clocking signal based on the control signal to generate a throttled clocking signal.
Dependencies are inferred from the claim text.