Controlling power delivery to a processor via a bypass

A method comprising:

• receiving, in a power controller of a multicore processor, target operating point requests for a plurality of cores of the multicore processor;
• in a second mode, controlling a control circuit of the multicore processor to provide a bypass voltage received via an external voltage rail to the plurality of cores to cause the plurality of cores to operate at the same or substantially the same operating voltage;
• in the second mode, disabling at least one integrated voltage regulator of the multicore processor;
• and
• in a first mode, controlling the control circuit to cause a first integrated voltage regulator to provide a regulated voltage to a first core of the plurality of cores.

A system on chip comprising:

• a semiconductor die including:
• a plurality of cores;
• a shared cache memory coupled to the plurality of cores;
• at least one internal voltage regulator to receive a first voltage from an external voltage regulator and provide a regulated voltage to at least one of the plurality of cores;
• a graphics processing unit;
• a fabric to couple the graphics processing unit and the plurality of cores;
• a Peripheral Component Interconnect Express interface;
• a circuit coupled to the at least one internal voltage regulator, wherein in a first mode the circuit is to cause the regulated voltage from the at least one internal voltage regulator to be provided to at least some of the plurality of cores, and in a second mode to cause a bypass voltage from the external voltage regulator to be provided to the at least some of the plurality of cores;
• and
• a power controller to determine an operating voltage for the plurality of cores, wherein in the second mode, the power controller is to cause the bypass voltage to be provided to the at least some of the plurality of cores and cause the at least one internal voltage regulator to be bypassed.