US 11,687,115 B2Granted

Precise time management for peripheral device using local time base

AssigneeApple Inc.

InventorsChristopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Kalpana Bansal, Michael Bekerman, Remi Clavel

Life of this patent

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Abstract

An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.

Claims20

Dependent claims

An apparatus comprising:

a peripheral interface circuit configured to receive information from a host circuit over a peripheral bus, wherein the host circuit is configured to maintain a global timebase in accordance with a first clock signal within a first clock domain, and wherein the peripheral interface circuit is configured to maintain, according to a second clock signal within a second clock domain, a first local timebase that is correlated to the global timebase;
a peripheral control circuit coupled to the peripheral interface circuit and configured to operate within a third clock domain, wherein the peripheral control circuit is configured to maintain, based on the first local timebase, a second local timebase, wherein the peripheral interface circuit is configured to determine phase and frequency differences between the second clock signal and the third clock signal in order to determine a correlation between the second local timebase and the first local timebase;
and
a peripheral logic circuit configured to operate within the third clock domain to perform, using a third local clock signal, operations that utilize a timestamp from the second local timebase, wherein the timestamp from the second local timebase accounts for correlation with the first local timebase.

1 more element

A method comprising:

receiving, at a peripheral interface circuit of a peripheral device, information regarding a global timebase from a host circuit over a peripheral bus, the global timebase being maintained by the host circuit in accordance with a first clock signal in a first clock domain;
maintaining, in accordance with a second clock signal in a second clock domain in the peripheral circuit, a first local timebase, wherein the maintaining includes correlating the first local timebase to the global timebase using the peripheral interface circuit;
maintaining a second global timebase in a peripheral control circuit coupled to the peripheral interface circuit, the peripheral control circuit operating in accordance with a third clock signal in a third clock domain;
determining, using the peripheral interface circuit, phase and frequency differences between the second clock signal and the third clock signal in order to determine a correlation between a second local timebase and the first local timebase;
and
operating a peripheral logic circuit in the third clock domain to perform operations utilizing a timestamp from the second local timebase, wherein the timestamp from the second local timebase accounts for correlation with the first local timebase.

3 more elements

A system comprising:

a host circuit, wherein the host circuit is configured to maintain a global timebase in accordance with a first clock signal having a first frequency;
and
a peripheral device coupled to the host circuit via a peripheral bus, wherein the peripheral device includes:
an interface circuit configured to maintain a first local timebase in accordance with a second clock signal having a second frequency, wherein the interface circuit is configured to correlate the first local timebase to the global timebase;
a control circuit configured to maintain a second local timebase in accordance with a third clock signal having a third frequency, wherein the interface circuit is configured to, in response to correlating the first local timebase to the global timebase, correlate the second local timebase to the first local timebase;
and
a logic circuit configured to perform operations that utilize a timestamp from the second local timebase, wherein the second local timebase accounts for the correlation with the first local timebase.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/482,178Filed 22 Sep 2021
Published: US 2023/0091434 A123 Mar 2023
Granted: 27 Jun 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 1/06
Generating or distributing clock signals or signals derived directly therefrom: clock generators producing several clock signals
G06F 1/14
Generating or distributing clock signals or signals derived directly therefrom: time supervision arrangements, e.g. real time clock
G06F 13/423
Being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus: with synchronous protocol
G06F
Computing and data processing