Automatic optimization of an examination recipe

A computerized method of automatic optimization of an examination recipe usable for semiconductor specimen examination, the method performed by a processing and memory circuitry (PMC) and comprising:

• obtaining, from a plurality of inspection tools, inspection data of a semiconductor specimen acquired during runtime examination, the inspection data comprising, for each inspection tool of the plurality of inspection tools, one or more inspection images representative of one or more defect candidates selected from a defect map of the semiconductor specimen using a classifier included in the examination recipe of the inspection tool;
• obtaining, from a review tool, label data informative of types of the one or more defect candidates;
• selecting a working point based on a plurality of performance measure parameters comprising at least one tool-to-tool difference parameter indicative of variance among the plurality of inspection tools;
• retraining, in parallel to the runtime examination, the classifier based on the working point using training data comprising inspection features characterizing the one or more inspection images of each inspection tool and the label data thereof, giving rise to a retrained classifier;
• and
• replacing the classifier with the retrained classifier to obtain an optimized examination recipe, the optimized examination recipe having improved robustness with respect to the variance among the plurality of inspection tools.

A non-transitory computer readable storage medium tangibly embodying a program of instructions that, when executed by a computer, cause the computer to perform a method of automatic optimization of an examination recipe usable for semiconductor specimen examination, the method comprising:

• obtaining, from a plurality of inspection tools, inspection data of a semiconductor specimen acquired during runtime examination, the inspection data comprising, for each inspection tool of the plurality of inspection tools, one or more inspection images representative of one or more defect candidates selected from a defect map of the semiconductor specimen using a classifier included in the examination recipe of the inspection tool;
• obtaining, from a review tool, label data informative of types of the one or more defect candidates;
• selecting a working point based on a plurality of performance measure parameters comprising at least one tool-to-tool difference parameter indicative of variance among the plurality of inspection tools;
• retraining, in parallel to the runtime examination, the classifier based on the working point using training data comprising inspection features characterizing the one or more inspection images of each inspection tool and the label data thereof, giving rise to a retrained classifier;
• and
• replacing the classifier with the retrained classifier to obtain an optimized examination recipe, the optimized examination recipe having improved robustness with respect to the variance among the plurality of inspection tools.