US 11,681,532 B2 · Method for forming constant extensions in the same execute packet in a VLIW processor

Abstract

In a very long instruction word (VLIW) central processing unit instructions are grouped into execute packets that execute in parallel. A constant may be specified or extended by bits in a constant extension instruction in the same execute packet. If an instruction includes an indication of constant extension, the decoder employs bits of a constant extension instruction to extend the constant of an immediate field. Two or more constant extension slots are permitted in each execute packet, each extending constants for a different predetermined subset of functional unit instructions. In an alternative embodiment, more than one functional unit may have constants extended from the same constant extension instruction employing the same extended bits. A long extended constant may be formed using the extension bits of two constant extension instructions.

Claims19

Dependent claims

A processor comprising:

a functional unit;
and
an instruction decoder coupled to the functional unit and configured to:
receive a first instruction that includes:
a first field that specifies an operation;
a second field that specifies a first value;
and
a third field that specifies whether to extend the first value based on a second instruction;
receive the second instruction, wherein the second instruction includes a fourth field that specifies a second value;
and
in response to the third field specifying to extend the first value based on the second instruction:
append the second value to the first value to form a third value;
sign extend the third value based on whether the first instruction is a scalar instruction or a vector instruction;
and
provide the third value to the functional unit for performing the operation specified by the first field.

12 more elements

A device comprising:

a functional unit;
and
an instruction decoder coupled to the functional unit and configured to:
receive a first instruction that includes:
a first field that specifies an operation;
a second field that specifies a first value;
and
a third field that specifies whether to extend the first value;
receive a second instruction, wherein the second instruction includes a fourth field that specifies a second value;
receive a third instruction, wherein the third instruction includes a fifth field that specifies a third value;
based on the third field specifying to extend the first value, form a fourth value based on appending the second value and the third value to the first value;
based on the third field specifying not to extend the first value, form the fourth value based on the first value and not the second value and the third value;
sign extend the fourth value to form a sign extended fourth value based on an instruction type of the first instruction;
and
provide the sign extended fourth value to the functional unit for performing the operation specified by the first field.

12 more elements

Dependencies are inferred from the claim text.

Method for forming constant extensions in the same execute packet in a VLIW processor

Life of this patent

Method for forming constant extensions in the same execute packet in a VLIW processor

Life of this patent

Abstract

Claims19