US 11,677,662 B2 · FPGA-efficient directional two-dimensional router

Abstract

A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The router and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.

Claims20

Dependent claims

A message router, comprising:

a first message input configured to receive a first message,
a second message input configured to receive a second message,
a third message input configured to receive a third message,
a first message output,
a second message output, and
a circuit comprising a dual-output lookup table of the field-programmable gate array and configured to couple one of the first, the second, and the third messages to the first message output, wherein coupling the one of the first, the second, and the third messages to the first message output and coupling the one of the first, the second, and the third messages to the second message output
comprises:
receiving, at the dual-output lookup table, one bit of the first message, one bit of the second message, and one bit of the third message;
selecting, with the dual-output lookup table, at least one of each of the one bits;
providing one selected bit to the first message output;
and
providing one selected bit to the second message output.

9 more elements

A non-transitory machine readable medium storing configuration data that when loaded into a field-programmable gate array, causes the field-programmable gate array to instantiate a message router, comprising:

a first message input configured to receive a first message,
a second message input configured to receive a second message,
a third message input configured to receive a third message,
a first message output,
a second message output, and
a first circuit comprising a dual-output lookup table of the field-programmable gate array and configured to couple one of the first, the second, and the third messages to the first message output and to couple one of the first, the second, and the third messages to the second message output, wherein coupling the one of the first, the second, and the third messages to the first message output and couple the one of the first, the second, and the third messages to the second message output comprises:
receive, at the dual-output lookup table, one bit of the first message, one bit of the second message, and one bit of the third message;
select, with the dual-output lookup table, at least one of each of the one bits;
provide one selected bit to the first message output;
and
provide one selected bit to the second message output.

8 more elements

Dependencies are inferred from the claim text.

FPGA-efficient directional two-dimensional router

Life of this patent

FPGA-efficient directional two-dimensional router

Life of this patent

Abstract

Claims20