Nanowire transistor fabrication with hardmask layers

A method of forming a microelectronic structure, comprising:

• forming a plurality of channel material layers over a microelectronic substrate,
• forming a sacrificial material layer between two of the plurality of channel material layers,
• forming a hardmask layer on a top surface of a first channel material layer of the plurality of channel material layers, wherein the first channel material layer is the farthest of the plurality of channel material layers from the microelectronic substrate;
• forming spacers on at least a part of the hardmask layer;
• selectively removing the sacrificial material layer between the two channel material layers to form a nanowire channel from the plurality of channel material layers, wherein the hardmask layer protects the first channel material layer during the selectively removing of the sacrificial material layer;
• selectively removing the hardmask layer from between the spacers after selectively removing the sacrificial material layer between the two channel material layers to leave a portion of the hardmask layer within the spacers and on top of a nanowire channel top surface farthest from the microelectronic substrate;
• forming a source structure and a drain structure over the microelectronic substrate on opposing ends of the plurality of channel material layers,
• forming a gate dielectric material to surround the nanowire channel between the spacers, and
• forming a gate electrode material on the gate dielectric material, wherein,
• the hardmask layer comprises at least one material selected from a group consisting of silicon, porous silicon, amorphous silicon, silicon nitride, silicon oxynitride, silicon oxide, silicon dioxide, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum silicate, lanthanum oxide, and polymer materials.