Method and apparatus for remote field programmable gate array processing
AssigneeIntel Corporation
InventorsNicolas A. Salhuana, Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Narayan Ranganathan
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Abstract
In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric.
Claims20
A network interface controller (NIC), comprising circuitry to:
- control access to a network fabric for a local processor;
- access data corresponding to respective kernels to program one or more field-programmable gate array (FPGA) accelerators locally communicatively coupled to the local processor;
- and
- receive, via the network fabric, an accelerator programming request, and determine whether a locally-available FPGA accelerator may service the accelerator programming request.
One or more non-transitory tangible computer-readable storage media having stored thereon instructions that, when executed, cause a circuit to be configured to, or instruct a programmable circuit to:
- facilitate communication between a local processor a network fabric that is to communicatively couple the local processor to a plurality of remote compute hosts;
- access a kernel table to store kernels to program one or more locally-available field-programmable gate array (FPGA) accelerators communicatively coupled to the local processor;
- and
- register one or more kernels for programming on the one or more locally-available FPGA accelerators.
A method of regulating access between a field-programmable gate array (FPGA) accelerator bank locally coupled to a local processor, and remote hosts coupled to the local processor via a network fabric, comprising:
- accessing a kernel table to store kernels to program one or more accelerators of the accelerator bank, wherein the accelerator bank includes one or more locally-available FPGA accelerators;
- registering one or more kernels for programming on the one or more accelerators of the accelerator bank;
- receiving, on a network interface controller (NIC), an FPGA kernel from a remote host;
- and
- programming, via the NIC, an FPGA of the accelerator bank with the FPGA kernel.
Dependencies are inferred from the claim text.