Reduced complexity decoder with improved error correction and related systems methods and devices

A method of decoding a low density parity check (LDPC) frame, the method comprising:

• receiving, at a physical layer device, the LDPC frame including known bits and unknown bits, the known bits having known values;
• passing log-likelihood ratio (LLR) messages between check nodes and message nodes, the message nodes corresponding to the known bits and the unknown bits, the check nodes corresponding to parity check equations of a parity check matrix, the LLR messages indicating probabilities that the known bits and the unknown bits have predetermined logic values;
• and
• saturating LLR values of at least a portion of the LLR messages corresponding to the known bits to a highest possible magnitude at a start of each sub-iteration of passing the LLR messages between the check nodes and the message nodes.

An apparatus, comprising:

• a terminal to receive a low density parity check (LDPC) frame, the LDPC frame including bits having log likelihood ratio (LLR) values associated therewith, a portion of the bits having known values, the LLR values indicating probabilities that the bits have predetermined logic values;
• and
• a processing circuitry to:
• correct bits of the LDPC frame using message nodes and check nodes responsive to at least the LLR values, the message nodes corresponding to the bits, the check nodes corresponding to parity check equations of a parity check matrix;
• and
• saturate a subset of the LLR values corresponding to the portion of the bits having the known values to a highest possible magnitude at a start of each sub-iteration.