Voltage-glitch detection and protection circuit for secure memory devices

A circuit comprising:

• a voltage-glitch-detection-block including:
• a voltage-glitch-detector operable to detect a voltage-glitch in a supply voltage (VDD) and generate a voltage-glitch-detection-pulse (PULSE);
• and
• a first latch having a set input coupled to the voltage-glitch-detector, the first latch operable to receive the PULSE and generate a first voltage-glitch-detection-pulse-latched (first PULSE_LATCHED) signal;
• and
• a system reset block coupled the voltage-glitch-detector and the first latch to receive the PULSE and the first PULSE_LATCHED signal, and to generate a secure system reset signal that causes a number of on-chip-circuits in a chip including the circuit to be reset,
• wherein the system reset block comprises a first level-detector coupled to receive the PULSE and the first PULSE_LATCHED signal, the first level-detector operable to generate the secure system reset signal, and
• wherein the system reset block further comprises a second level-detector coupled to VDD, and, through a logic gate, to a controller, wherein:
• the second level-detector is operable to detect a drop in VDD below a predetermined minimum supply voltage (VDDMIN) and generate a non-secure system reset signal;
• the logic gate is operable to receive non-secure system reset signal from the second level-detector and the secure system reset signal from the first level-detector generate a system-reset-signal to the controller;
• and
• the controller is operable to generate one or more global-reset-signals to reset the number of on-chip-circuits in the chip.

A system comprising:

• an embedded non-volatile memory;
• a circuit comprising:
• a voltage-glitch-detection-block including:
• a voltage-glitch-detector operable to detect a voltage-glitch in a supply voltage (VDD) and generate a voltage-glitch-detection-pulse (PULSE);
• and
• a latch having a set input coupled to the voltage-glitch-detector, the
• latch operable to receive the PULSE and generate a voltage-glitch-detection-pulse-latched (PULSE_LATCHED) signal;
• and
• a system reset block coupled the voltage-glitch-detector and the latch to receive the PULSE and the PULSE_LATCHED signal, and to generate a secure system reset signal to reset the embedded non-volatile memory, the system reset block comprising:
• a first level-detector coupled to receive the PULSE and the PULSE_LATCHED signal, the first level-detector operable to generate the secure system reset signal;
• and
• a second level-detector coupled to VDD, and, through a logic gate, to a controller, wherein the second level-detector is operable to detect a drop in VDD below a predetermined minimum supply voltage (VDDMIN) and generate a non-secure system reset signal;
• wherein the voltage-glitch-detector comprises a comparator having a first input coupled to VDD and a second input coupled to a reference voltage (VREF) based on a predetermined setpoint voltage (VGLITCH), the comparator operable to compare VDD to VREF, and wherein the voltage-glitch-detector is operable to generate the PULSE when VDD<VREF, and
• wherein the latch is a voltage-glitch-protected-latch comprising a first voltage-glitch-isolation filter (GIF) and a sample and hold (S&H) circuit through which the voltage-glitch-protected-latch is coupled to VDD to provide a voltage (VDDRC S&H) to power the voltage-glitch-protected-latch when VDD drops below VGLITCH.